Skip to content

Commit 0d627b4

Browse files
fix: tests part 7, should work now
1 parent a0ad409 commit 0d627b4

3 files changed

Lines changed: 27 additions & 12 deletions

File tree

Inc/MockedDrivers/mocked_ll_tim.hpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,10 +119,13 @@ class TIM_TypeDef{
119119
}
120120
return true;
121121
}
122+
123+
void inc_cnt_and_check(uint32_t val);
122124
};
123125
static_assert(sizeof(TimerRegister<Reg_CNT>) == sizeof(uint32_t));
124126
void simulate_ticks(TIM_TypeDef* tim);
125127

128+
/*
126129
template<>
127130
struct RegisterTraits<TimReg,TimReg::Reg_CNT> {
128131
static void write(uint32_t& target, uint32_t val) {
@@ -133,7 +136,7 @@ struct RegisterTraits<TimReg,TimReg::Reg_CNT> {
133136
}
134137
}
135138
};
136-
139+
*/
137140

138141
#define DECLARE_TIMER(TIM_IDX) \
139142
extern TIM_TypeDef* TIM_IDX##_BASE; \

Src/MockedDrivers/mocked_ll_tim.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ void TIM_TypeDef::generate_update() {
1010
active_RCR = RCR;
1111
internal_rcr_cnt = active_RCR;
1212
internal_psc_cnt = 0;
13-
CNT = 0; // Usually UEV also resets CNT unless configured otherwise
13+
*((uint32_t*)&CNT) = 0; // Usually UEV also resets CNT unless configured otherwise
1414
SR &= ~(1U << 0); // Clear UIF if needed, or set it depending on CR1
1515
}
1616
void simulate_ticks(TIM_TypeDef* tim){
@@ -58,4 +58,11 @@ void simulate_ticks(TIM_TypeDef* tim){
5858
tim->internal_rcr_cnt--;
5959
}
6060
}
61+
}
62+
63+
void TIM_TypeDef::inc_cnt_and_check(uint32_t val) {
64+
if(val != 0 && this->check_CNT_increase_preconditions()){
65+
this->CNT += val;
66+
simulate_ticks(this);
67+
}
6168
}

Tests/Time/scheduler_test.cpp

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -44,12 +44,11 @@ TEST_F(SchedulerTests, TaskRegistration) {
4444
TEST_F(SchedulerTests, TaskExecutionShort) {
4545
Scheduler::register_task(10,&fake_workload);
4646
Scheduler::start();
47-
// TIM2_BASE->ARR = 500;
48-
// TIM2_BASE->generate_update();
47+
TIM2_BASE->PSC = 2; // quicker test
4948

5049
constexpr int NUM_TICKS = 1'000;
5150
for(int i = 0; i < NUM_TICKS; i++){
52-
TIM2_BASE->CNT++;
51+
for(int j = 0; j <= TIM2_BASE->PSC; j++) TIM2_BASE->inc_cnt_and_check(1);
5352
Scheduler::update();
5453
}
5554
// 1000 ticks / 10 ticks/task = 100 executions.
@@ -61,10 +60,11 @@ TEST_F(SchedulerTests, TaskExecutionLong) {
6160
Scheduler::start();
6261
// TIM2_BASE->ARR = 500;
6362
TIM2_BASE->generate_update();
63+
TIM2_BASE->PSC = 2; // quicker test
6464

6565
constexpr int NUM_TICKS = 1'000'000;
6666
for(int i = 0; i < NUM_TICKS; i++){
67-
TIM2_BASE->CNT++;
67+
for(int j = 0; j <= TIM2_BASE->PSC; j++) TIM2_BASE->inc_cnt_and_check(1);
6868
Scheduler::update();
6969
}
7070
EXPECT_EQ(count, 100'000);
@@ -73,10 +73,11 @@ TEST_F(SchedulerTests, TaskExecutionLong) {
7373
TEST_F(SchedulerTests, SetTimeout) {
7474
Scheduler::set_timeout(10, &fake_workload);
7575
Scheduler::start();
76-
76+
TIM2_BASE->PSC = 2; // quicker test
77+
7778
constexpr int NUM_TICKS = 100;
7879
for(int i = 0; i < NUM_TICKS; i++){
79-
TIM2_BASE->CNT++;
80+
for(int j = 0; j <= TIM2_BASE->PSC; j++) TIM2_BASE->inc_cnt_and_check(1);
8081
Scheduler::update();
8182
}
8283
EXPECT_EQ(count, 1);
@@ -86,10 +87,12 @@ TEST_F(SchedulerTests, GlobalTickOverflow) {
8687
Scheduler::global_tick_us_ = 0xFFFFFFF0ULL; // Near 32-bit max
8788
Scheduler::register_task(20, &fake_workload);
8889
Scheduler::start();
89-
90+
TIM2_BASE->PSC = 2; // quicker test
91+
9092
constexpr int NUM_TICKS = 100;
9193
for(int i = 0; i < NUM_TICKS; i++){
92-
TIM2_BASE->CNT++;
94+
for(int j = 0; j <= TIM2_BASE->PSC; j++) TIM2_BASE->inc_cnt_and_check(1);
95+
9396
Scheduler::update();
9497
}
9598
// 100 ticks /20 ticks/task = 5 executions.
@@ -99,10 +102,11 @@ TEST_F(SchedulerTests, GlobalTickOverflow) {
99102
TEST_F(SchedulerTests, TimeoutClearAddTask) {
100103
uint8_t timeout_id = Scheduler::set_timeout(10, &fake_workload);
101104
Scheduler::start();
105+
TIM2_BASE->PSC = 2; // quicker test
102106

103107
constexpr int NUM_TICKS = 100;
104108
for(int i = 0; i < NUM_TICKS; i++) {
105-
TIM2_BASE->CNT++;
109+
for(int j = 0; j <= TIM2_BASE->PSC; j++) TIM2_BASE->inc_cnt_and_check(1);
106110
Scheduler::update();
107111
}
108112

@@ -135,10 +139,11 @@ TEST_F(SchedulerTests, TaskDe_ReRegistration) {
135139
uint8_t operational_task = 0;
136140
uint8_t fault_task = 0;
137141
Scheduler::start();
142+
TIM2_BASE->PSC = 2; // quicker test
138143

139144
constexpr int NUM_TICKS = 100;
140145
for(int i = 0; i < NUM_TICKS; i++) {
141-
TIM2_BASE->CNT++;
146+
for(int j = 0; j <= TIM2_BASE->PSC; j++) TIM2_BASE->inc_cnt_and_check(1);
142147
if(i == 21){
143148
Scheduler::unregister_task(connecting_task);
144149
operational_task = Scheduler::register_task(10,operational_cyclic);

0 commit comments

Comments
 (0)