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FoniksFoxFoniksFox
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feat(MPU): Use absolute values rather than addresses and casts for Linker Symbols, also clean up LD scripts
1 parent cf94046 commit 3676cf5

3 files changed

Lines changed: 122 additions & 133 deletions

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‎Inc/HALAL/Models/MPU.hpp‎

Lines changed: 34 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -54,28 +54,28 @@
5454
#define RAM_CODE __attribute__((section(".ram_code")))
5555

5656
// Memory Bank Symbols from Linker
57-
extern "C" uint32_t __itcm_base;
58-
extern "C" uint32_t __itcm_size;
59-
extern "C" uint32_t __dtcm_base;
60-
extern "C" uint32_t __dtcm_size;
61-
extern "C" uint32_t __flash_base;
62-
extern "C" uint32_t __flash_size;
63-
extern "C" uint32_t __ram_d1_base;
64-
extern "C" uint32_t __ram_d1_size;
65-
extern "C" uint32_t __ram_d2_base;
66-
extern "C" uint32_t __ram_d2_size;
67-
extern "C" uint32_t __ram_d3_base;
68-
extern "C" uint32_t __ram_d3_size;
69-
extern "C" uint32_t __peripheral_base;
70-
extern "C" uint32_t __peripheral_size;
57+
extern "C" const uintptr_t __itcm_base;
58+
extern "C" const size_t __itcm_size;
59+
extern "C" const uintptr_t __dtcm_base;
60+
extern "C" const size_t __dtcm_size;
61+
extern "C" const uintptr_t __flash_base;
62+
extern "C" const size_t __flash_size;
63+
extern "C" const uintptr_t __ram_d1_base;
64+
extern "C" const size_t __ram_d1_size;
65+
extern "C" const uintptr_t __ram_d2_base;
66+
extern "C" const size_t __ram_d2_size;
67+
extern "C" const uintptr_t __ram_d3_base;
68+
extern "C" const size_t __ram_d3_size;
69+
extern "C" const uintptr_t __peripheral_base;
70+
extern "C" const size_t __peripheral_size;
7171

7272
// MPU Non-Cached Section Symbols from Linker
73-
extern "C" uint32_t __mpu_d1_nc_start;
74-
extern "C" uint32_t __mpu_d1_nc_end;
75-
extern "C" uint32_t __mpu_d2_nc_start;
76-
extern "C" uint32_t __mpu_d2_nc_end;
77-
extern "C" uint32_t __mpu_d3_nc_start;
78-
extern "C" uint32_t __mpu_d3_nc_end;
73+
extern "C" const uintptr_t __mpu_d1_nc_start;
74+
extern "C" const uintptr_t __mpu_d1_nc_end;
75+
extern "C" const uintptr_t __mpu_d2_nc_start;
76+
extern "C" const uintptr_t __mpu_d2_nc_end;
77+
extern "C" const uintptr_t __mpu_d3_nc_start;
78+
extern "C" const uintptr_t __mpu_d3_nc_end;
7979

8080

8181
template <typename T>
@@ -288,9 +288,9 @@ struct MPUDomain {
288288
configure_static_regions();
289289

290290
// Dynamic Configuration based on Linker Symbols
291-
configure_dynamic_region((uint32_t)&__mpu_d1_nc_start, (uint32_t)&__mpu_d1_nc_end, MPU_REGION_NUMBER3);
292-
configure_dynamic_region((uint32_t)&__mpu_d2_nc_start, (uint32_t)&__mpu_d2_nc_end, MPU_REGION_NUMBER5);
293-
configure_dynamic_region((uint32_t)&__mpu_d3_nc_start, (uint32_t)&__mpu_d3_nc_end, MPU_REGION_NUMBER7);
291+
configure_dynamic_region((uintptr_t)__mpu_d1_nc_start, (uintptr_t)__mpu_d1_nc_end, MPU_REGION_NUMBER3);
292+
configure_dynamic_region((uintptr_t)__mpu_d2_nc_start, (uintptr_t)__mpu_d2_nc_end, MPU_REGION_NUMBER5);
293+
configure_dynamic_region((uintptr_t)__mpu_d3_nc_start, (uintptr_t)__mpu_d3_nc_end, MPU_REGION_NUMBER7);
294294

295295
// Assign pointers
296296
uint8_t* bases_nc[3] = { &d1_nc_buffer[0], &d2_nc_buffer[0], &d3_nc_buffer[0] };
@@ -321,7 +321,7 @@ struct MPUDomain {
321321
private:
322322
static constexpr std::size_t alignments[6] = {32, 16, 8, 4, 2, 1};
323323

324-
static void configure_dynamic_region(uint32_t start, uint32_t end, uint8_t region_num) {
324+
static void configure_dynamic_region(uintptr_t start, uintptr_t end, uint8_t region_num) {
325325
if (end <= start) return;
326326
configure_region(start, end - start, region_num,
327327
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_DISABLE,
@@ -348,47 +348,47 @@ struct MPUDomain {
348348

349349
// Peripherals (Device, Buffered)
350350
// Guarded against speculative execution and cache
351-
configure_region((uint32_t)&__peripheral_base, (uint32_t)&__peripheral_size, MPU_REGION_NUMBER8,
351+
configure_region(__peripheral_base, __peripheral_size, MPU_REGION_NUMBER8,
352352
MPU_TEX_LEVEL0, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_DISABLE,
353353
MPU_ACCESS_SHAREABLE, MPU_ACCESS_NOT_CACHEABLE, MPU_ACCESS_BUFFERABLE);
354354

355355
// Flash (Normal, Cacheable)
356356
// TEX=1, C=1, B=0: Normal, Write-Through (Read optimized)
357357
// Not Shareable to allow full caching
358-
configure_region((uint32_t)&__flash_base, (uint32_t)&__flash_size, MPU_REGION_NUMBER1,
358+
configure_region(__flash_base, __flash_size, MPU_REGION_NUMBER1,
359359
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_ENABLE,
360360
MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_CACHEABLE, MPU_ACCESS_NOT_BUFFERABLE);
361361

362362
// DTCM (Normal, Cacheable)
363363
// Uses Normal memory attributes. TCM access is uncached by hardware, but "Normal" allows unaligned access.
364-
configure_region((uint32_t)&__dtcm_base, (uint32_t)&__dtcm_size, MPU_REGION_NUMBER10,
364+
configure_region(__dtcm_base, __dtcm_size, MPU_REGION_NUMBER10,
365365
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_DISABLE,
366366
MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_CACHEABLE, MPU_ACCESS_BUFFERABLE);
367367

368368
// ITCM (Normal, Cacheable)
369-
configure_region((uint32_t)&__itcm_base, (uint32_t)&__itcm_size, MPU_REGION_NUMBER11,
369+
configure_region(__itcm_base, __itcm_size, MPU_REGION_NUMBER11,
370370
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_ENABLE,
371371
MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_CACHEABLE, MPU_ACCESS_BUFFERABLE);
372372

373373
// D1 RAM Cached (Normal, WBWA)
374374
// TEX=1, C=1, B=1: Normal, Write-Back, Write-Allocate
375375
// Not Shareable ensures strict L1 utilization.
376-
configure_region((uint32_t)&__ram_d1_base, (uint32_t)&__ram_d1_size, MPU_REGION_NUMBER2,
376+
configure_region(__ram_d1_base, __ram_d1_size, MPU_REGION_NUMBER2,
377377
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_DISABLE,
378378
MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_CACHEABLE, MPU_ACCESS_BUFFERABLE);
379379

380380
// D2 RAM Cached (Normal, WBWA)
381-
configure_region((uint32_t)&__ram_d2_base, (uint32_t)&__ram_d2_size, MPU_REGION_NUMBER4,
381+
configure_region(__ram_d2_base, __ram_d2_size, MPU_REGION_NUMBER4,
382382
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_DISABLE,
383383
MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_CACHEABLE, MPU_ACCESS_BUFFERABLE);
384384

385385
// D3 RAM Cached (Normal, WBWA)
386-
configure_region((uint32_t)&__ram_d3_base, (uint32_t)&__ram_d3_size, MPU_REGION_NUMBER6,
386+
configure_region(__ram_d3_base, __ram_d3_size, MPU_REGION_NUMBER6,
387387
MPU_TEX_LEVEL1, MPU_REGION_FULL_ACCESS, MPU_INSTRUCTION_ACCESS_DISABLE,
388388
MPU_ACCESS_NOT_SHAREABLE, MPU_ACCESS_CACHEABLE, MPU_ACCESS_BUFFERABLE);
389389
}
390390

391-
static void configure_region(uint32_t base, uint32_t size, uint8_t region_num,
391+
static void configure_region(uintptr_t base, size_t size, uint8_t region_num,
392392
uint8_t tex, uint8_t access, uint8_t no_exec,
393393
uint8_t shareable, uint8_t cacheable, uint8_t bufferable) {
394394
if (size == 0) return;
@@ -400,7 +400,7 @@ struct MPUDomain {
400400
if (size > 32) {
401401
// Calculate ceil(log2(size)) - 1
402402
// __builtin_clz(x) returns leading zeros. For 32, it's 26: 31 - 26 = 5
403-
mpu_size = 31 - __builtin_clz(size - 1);
403+
mpu_size = (sizeof(size) * 8 - 1) - __builtin_clz(size - 1);
404404
}
405405

406406
// Calculate SubRegion Disable (SRD)
@@ -414,7 +414,7 @@ struct MPUDomain {
414414
MPU_Region_InitTypeDef MPU_InitStruct = {0};
415415
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
416416
MPU_InitStruct.Number = region_num;
417-
MPU_InitStruct.BaseAddress = base;
417+
MPU_InitStruct.BaseAddress = static_cast<decltype(MPU_InitStruct.BaseAddress)>(base); // Should be uint32_t, but may be different when mocking, so this is just to make sure it accepts it
418418
MPU_InitStruct.Size = mpu_size;
419419
MPU_InitStruct.SubRegionDisable = srd;
420420
MPU_InitStruct.TypeExtField = tex;

‎STM32H723ZGTX_FLASH.ld‎

Lines changed: 20 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -55,20 +55,20 @@ MEMORY
5555
SECTIONS
5656
{
5757
/* Export Memory Layout Information for MPU Configuration */
58-
PROVIDE(__itcm_base = ORIGIN(ITCMRAM));
59-
PROVIDE(__itcm_size = LENGTH(ITCMRAM));
60-
PROVIDE(__dtcm_base = ORIGIN(DTCMRAM));
61-
PROVIDE(__dtcm_size = LENGTH(DTCMRAM));
62-
PROVIDE(__flash_base = ORIGIN(FLASH));
63-
PROVIDE(__flash_size = LENGTH(FLASH));
64-
PROVIDE(__ram_d1_base = ORIGIN(RAM_D1));
65-
PROVIDE(__ram_d1_size = LENGTH(RAM_D1));
66-
PROVIDE(__ram_d2_base = ORIGIN(RAM_D2));
67-
PROVIDE(__ram_d2_size = LENGTH(RAM_D2));
68-
PROVIDE(__ram_d3_base = ORIGIN(RAM_D3));
69-
PROVIDE(__ram_d3_size = LENGTH(RAM_D3));
70-
PROVIDE(__peripheral_base = 0x40000000);
71-
PROVIDE(__peripheral_size = 0x20000000); /* 512MB */
58+
__itcm_base = ABSOLUTE(ORIGIN(ITCMRAM));
59+
__itcm_size = ABSOLUTE(LENGTH(ITCMRAM));
60+
__dtcm_base = ABSOLUTE(ORIGIN(DTCMRAM));
61+
__dtcm_size = ABSOLUTE(LENGTH(DTCMRAM));
62+
__flash_base = ABSOLUTE(ORIGIN(FLASH));
63+
__flash_size = ABSOLUTE(LENGTH(FLASH));
64+
__ram_d1_base = ABSOLUTE(ORIGIN(RAM_D1));
65+
__ram_d1_size = ABSOLUTE(LENGTH(RAM_D1));
66+
__ram_d2_base = ABSOLUTE(ORIGIN(RAM_D2));
67+
__ram_d2_size = ABSOLUTE(LENGTH(RAM_D2));
68+
__ram_d3_base = ABSOLUTE(ORIGIN(RAM_D3));
69+
__ram_d3_size = ABSOLUTE(LENGTH(RAM_D3));
70+
__peripheral_base = 0x40000000;
71+
__peripheral_size = 0x20000000; /* 512MB */
7272

7373
/* The startup code goes first into FLASH */
7474
.isr_vector :
@@ -138,7 +138,7 @@ SECTIONS
138138
.mpu_ram_d1_nc :
139139
{
140140
. = ALIGN(32);
141-
PROVIDE(__mpu_d1_nc_start = .);
141+
__mpu_d1_nc_start = ABSOLUTE(.);
142142

143143
/* New MPU system buffers */
144144
*(.mpu_ram_d1_nc.buffer)
@@ -161,7 +161,7 @@ SECTIONS
161161
_d1_pad = (_d1_size + _d1_sub - 1) / _d1_sub * _d1_sub;
162162
/* Advance current pointer to reserve this space */
163163
. = __mpu_d1_nc_start + _d1_pad;
164-
PROVIDE(__mpu_d1_nc_end = .);
164+
__mpu_d1_nc_end = ABSOLUTE(.);
165165

166166
/* used by the startup to initialize data */
167167
_sidata = LOADADDR(.data);
@@ -223,7 +223,7 @@ SECTIONS
223223
.mpu_ram_d2_nc :
224224
{
225225
. = ALIGN(32);
226-
PROVIDE(__mpu_d2_nc_start = .);
226+
__mpu_d2_nc_start = ABSOLUTE(.);
227227

228228
/* ETH Descriptors - Must be aligned */
229229
*(.RxDecripSection)
@@ -244,13 +244,13 @@ SECTIONS
244244
_d2_sub = _d2_p2 / 8;
245245
_d2_pad = (_d2_size + _d2_sub - 1) / _d2_sub * _d2_sub;
246246
. = __mpu_d2_nc_start + _d2_pad;
247-
PROVIDE(__mpu_d2_nc_end = .);
247+
__mpu_d2_nc_end = ABSOLUTE(.);
248248

249249
/* MPU D3 Non-Cached Section */
250250
.mpu_ram_d3_nc :
251251
{
252252
. = ALIGN(32);
253-
PROVIDE(__mpu_d3_nc_start = .);
253+
__mpu_d3_nc_start = ABSOLUTE(.);
254254

255255
/* New MPU system buffers */
256256
*(.mpu_ram_d3_nc.buffer)
@@ -271,7 +271,7 @@ SECTIONS
271271
_d3_sub = _d3_p2 / 8;
272272
_d3_pad = (_d3_size + _d3_sub - 1) / _d3_sub * _d3_sub;
273273
. = __mpu_d3_nc_start + _d3_pad;
274-
PROVIDE(__mpu_d3_nc_end = .);
274+
__mpu_d3_nc_end = ABSOLUTE(.);
275275

276276
/* Code running in ITCM RAM (0 Wait States, Instruction Bus) */
277277
.ram_code :
@@ -300,9 +300,6 @@ SECTIONS
300300
{
301301
. = ALIGN(32);
302302

303-
/* Legacy MPUManager allocations (if any) */
304-
*(.ram_d1.legacy)
305-
306303
/* User manual allocations via D1_C macro */
307304
*(.ram_d1.user)
308305

@@ -315,9 +312,6 @@ SECTIONS
315312
{
316313
. = ALIGN(32);
317314

318-
/* Legacy MPUManager allocations (if any) */
319-
*(.ram_d2.legacy)
320-
321315
/* User manual allocations via D2_C macro */
322316
*(.ram_d2.user)
323317

@@ -330,9 +324,6 @@ SECTIONS
330324
{
331325
. = ALIGN(32);
332326

333-
/* Legacy MPUManager allocations (if any) */
334-
*(.ram_d3.legacy)
335-
336327
/* User manual allocations via D3_C macro */
337328
*(.ram_d3.user)
338329

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