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add indentation for 14 time
1 parent c06bd0f commit 7af2239

4 files changed

Lines changed: 16 additions & 23 deletions

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.changesets/dfsdm-module-minor.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
11
release: minor
2-
summary: Added module dfsdm tested
2+
summary: Added module dfsdm tested

Inc/HALAL/Services/ADC/ADC.hpp

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -189,15 +189,7 @@ struct ADCDomain {
189189
ClockPrescaler prescaler = ClockPrescaler::DIV1,
190190
uint32_t sample_rate_hz = 0
191191
)
192-
: ADC(
193-
pin,
194-
resolution,
195-
sample_time,
196-
prescaler,
197-
sample_rate_hz,
198-
peripheral,
199-
channel
200-
) {}
192+
: ADC(pin, resolution, sample_time, prescaler, sample_rate_hz, peripheral, channel) {}
201193

202194
template <class Ctx> consteval std::size_t inscribe(Ctx& ctx) const {
203195
const auto gpio_idx = gpio.inscribe(ctx);

Inc/HALAL/Services/DFSDM/DFSDM.hpp

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -610,15 +610,15 @@ struct DFSDM_CHANNEL_DOMAIN {
610610
}
611611
}
612612
// validate buffers
613-
if(active_channels > 1 && entries[i].config_filter.type_conv == Type_Conversion::Regular){
613+
if (active_channels > 1 &&
614+
entries[i].config_filter.type_conv == Type_Conversion::Regular) {
614615
compile_error("Not allowed more than 1 channel per filter in Regular Mode");
615616
}
616617
if (active_channels > 1 && cfgs[i].dma_enable == Dma::Enable) {
617618
// Look the entry because the data that I want to check is easier to access
618619
if (entries[i].config_filter.jscan == Injected_Mode::Single) {
619-
compile_error(
620-
"Not allowed more than 1 channel per filter + Injected_Mode::Single_conversion"
621-
);
620+
compile_error("Not allowed more than 1 channel per filter + "
621+
"Injected_Mode::Single_conversion");
622622
}
623623
for (size_t j = 0; j < 8; j++) {
624624
if (channels_filter[cfgs[i].filter][j] > 1) {
@@ -724,13 +724,15 @@ struct DFSDM_CHANNEL_DOMAIN {
724724
DFSDM1_Channel6,
725725
DFSDM1_Channel7
726726
};
727-
static void inline start_reg_conv_filter(uint8_t filter){
728-
if(filter > 3) ErrorHandler("Only filters from 0..3");
727+
static void inline start_reg_conv_filter(uint8_t filter) {
728+
if (filter > 3)
729+
ErrorHandler("Only filters from 0..3");
729730
filter_hw[filter]->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; // regular
730731
}
731-
static void inline start_inj_conv_filter(uint8_t filter){
732-
if(filter > 3) ErrorHandler("Only filters from 0..3");
733-
filter_hw[filter]->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; // injected
732+
static void inline start_inj_conv_filter(uint8_t filter) {
733+
if (filter > 3)
734+
ErrorHandler("Only filters from 0..3");
735+
filter_hw[filter]->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; // injected
734736
}
735737
static DMADomain::Instance*
736738
find_dma_instance(uint32_t request, std::span<DMADomain::Instance> dma_peripherals) {
@@ -897,14 +899,15 @@ struct DFSDM_CHANNEL_DOMAIN {
897899
"channel buffer");
898900
}
899901
return (
900-
static_cast<int32_t>(this->buffer[pos] & DFSDM_FLTJDATAR_JDATA_Msk) >> DFSDM_FLTJDATAR_JDATA_Pos
902+
static_cast<int32_t>(this->buffer[pos] & DFSDM_FLTJDATAR_JDATA_Msk) >>
903+
DFSDM_FLTJDATAR_JDATA_Pos
901904
); // The constants values are the same for regular than injected
902905
}
903906
int32_t read() {
904907
return (
905908
static_cast<int32_t>(this->buffer[0] & DFSDM_FLTJDATAR_JDATA_Msk) >>
906909
DFSDM_FLTJDATAR_JDATA_Pos
907-
);
910+
);
908911
}
909912
uint32_t check_latency_cycles() {
910913
return filter_regs->FLTCNVTIMR >> DFSDM_FLTCNVTIMR_CNVCNT_Pos;

Inc/ST-LIB.hpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -140,8 +140,6 @@ consteval std::array<DMADomain::Config, TotalN> build_dma_configs(
140140

141141
} // namespace BuildUtils
142142

143-
144-
145143
template <auto&... devs> struct Board {
146144
static consteval auto build_ctx() {
147145
DomainsCtx ctx{};

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