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feat(System): Move System.c to ST-LIB
1 parent 9e7670b commit 8cedb99

4 files changed

Lines changed: 206 additions & 1 deletion

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‎CMakeLists.txt‎

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@@ -414,6 +414,7 @@ add_library(${STLIB_LIBRARY} OBJECT
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$<$<AND:$<BOOL:${CMAKE_CROSSCOMPILING}>,$<BOOL:${USE_ETHERNET}>>:${HALAL_C_ETH_PHY}>
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$<$<BOOL:${CMAKE_CROSSCOMPILING}>:${CMAKE_CURRENT_LIST_DIR}/System.c>
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$<$<BOOL:${CMAKE_CROSSCOMPILING}>:${CPP_UTILITIES_C}>
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$<$<BOOL:${CMAKE_CROSSCOMPILING}>:${CPP_UTILITIES_CPP}>
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‎Inc/ST-LIB.hpp‎

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@@ -348,4 +348,17 @@ template <auto&... devs> struct Board {
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* before the global constructors and main() are called.
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* It is responsible for initializing the hardware and peripherals
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*/
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extern void BoardInit(void);
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief This is a function that gets called early in the startup process,
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* before the global constructors and main() are called.
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* It is responsible for initializing the hardware and peripherals
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*/
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void BoardInit(void);
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#ifdef __cplusplus
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}
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#endif

‎Src/ST-LIB.cpp‎

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@@ -50,3 +50,7 @@ void STLIB::update() {
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ErrorHandlerModel::ErrorHandlerUpdate();
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MDMA::update();
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}
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__attribute__((weak)) void BoardInit() {
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// Nothing for now
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}

‎System.c‎

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@@ -0,0 +1,187 @@
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#define BOOT_ATTR __attribute__((section(".boot"))) __used
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#include "stm32h7xx.h"
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#include <math.h>
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#if !defined(HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined(CSI_VALUE)
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#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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#if !defined(HSI_VALUE)
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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uint32_t SystemCoreClock = 64000000;
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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BOOT_ATTR void SystemInit(void) {
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__IO uint32_t tmpreg;
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SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Increasing the CPU frequency */
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if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) {
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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}
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/* Set HSION bit */
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RCC->CR |= RCC_CR_HSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
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RCC->CR &= 0xEAF6ED7FU;
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/* Decreasing the number of wait states because of lower CPU frequency */
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if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) {
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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}
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x02020200;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x01FF0000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x01010280;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x01010280;
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x01010280;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
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tmpreg = RCC->AHB2ENR;
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(void)tmpreg;
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/*
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* Disable the FMC bank1 (enabled after reset).
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* This, prevents CPU speculation access on this bank which blocks the use of FMC during
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* 24us. During this time the others FMC master (such as LTDC) cannot use it!
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*/
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FMC_Bank1_R->BTCR[0] = 0x000030D2;
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}
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BOOT_ATTR void SystemCoreClockUpdate(void) {
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uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
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uint32_t common_system_clock;
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float_t fracn1, pllvco;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS) {
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
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common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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break;
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case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
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common_system_clock = CSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
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common_system_clock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
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pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
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pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
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fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
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if (pllm != 0U) {
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switch (pllsource) {
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case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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pllvco = ((float_t)hsivalue / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) +
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(fracn1 / (float_t)0x2000) + (float_t)1);
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break;
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case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
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pllvco = ((float_t)CSI_VALUE / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) +
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(fracn1 / (float_t)0x2000) + (float_t)1);
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break;
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case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) +
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(fracn1 / (float_t)0x2000) + (float_t)1);
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break;
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default:
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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pllvco = ((float_t)hsivalue / (float_t)pllm) *
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((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) +
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(fracn1 / (float_t)0x2000) + (float_t)1);
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break;
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}
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pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
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common_system_clock = (uint32_t)(float_t)(pllvco / (float_t)pllp);
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} else {
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common_system_clock = 0U;
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}
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break;
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default:
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common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
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break;
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}
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tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
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/* common_system_clock frequency : CM7 CPU frequency */
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common_system_clock >>= tmp;
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/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
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SystemD2Clock =
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(common_system_clock >>
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((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
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SystemCoreClock = common_system_clock;
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}
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BOOT_ATTR void ConfigurationChecker() {
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// Nothing for now
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}

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