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victor-Lopez25victor-Lopez25
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Fix: Try to fix -Wchanges-meaning warning
1 parent 44e8d8c commit a3fc792

1 file changed

Lines changed: 38 additions & 36 deletions

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‎Inc/MockedDrivers/mocked_ll_tim.hpp‎

Lines changed: 38 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -5,22 +5,24 @@
55
#include "MockedDrivers/tim_register_definitions.hpp"
66
#include "MockedDrivers/Register.hpp"
77
#include <iostream>
8-
enum class TimRegs {
9-
CR1, CR2, SMCR, DIER, SR, EGR, CCMR1, CCMR2, CCER, CNT, PSC, ARR, RCR,
10-
CCR1, CCR2, CCR3, CCR4, BDTR, DCR, DMAR, CCMR3, CCR5, CCR6, AF1, AF2, TISEL
8+
enum class TimReg {
9+
Reg_CR1, Reg_CR2, Reg_SMCR, Reg_DIER, Reg_SR, Reg_EGR,
10+
Reg_CCMR1, Reg_CCMR2, Reg_CCER, Reg_CNT, Reg_PSC, Reg_ARR, Reg_RCR,
11+
Reg_CCR1, Reg_CCR2, Reg_CCR3, Reg_CCR4, Reg_BDTR, Reg_DCR,
12+
Reg_DMAR, Reg_CCMR3, Reg_CCR5, Reg_CCR6, Reg_AF1, Reg_AF2, Reg_TISEL
1113
};
12-
using enum TimRegs;
14+
using enum TimReg;
1315

1416

1517

16-
template<TimRegs Reg>
17-
class TimerRegister : public RegisterBase<TimRegs, Reg> {
18+
template<TimReg Reg>
19+
class TimerRegister : public RegisterBase<TimReg, Reg> {
1820
public:
19-
using RegisterBase<TimRegs, Reg>::RegisterBase;
20-
using RegisterBase<TimRegs, Reg>::operator=;
21+
using RegisterBase<TimReg, Reg>::RegisterBase;
22+
using RegisterBase<TimReg, Reg>::operator=;
2123
};
2224

23-
static_assert(sizeof(TimerRegister<TimRegs::CR1>) == sizeof(uint32_t) );
25+
static_assert(sizeof(TimerRegister<Reg_CR1>) == sizeof(uint32_t) );
2426

2527

2628
class TIM_TypeDef{
@@ -29,33 +31,33 @@ class TIM_TypeDef{
2931
callback{irq_handler},irq_n{irq_n}
3032
{}
3133
void generate_update();
32-
TimerRegister<CR1> CR1; /*!< TIM control register 1, Address offset: 0x00 */
33-
TimerRegister<CR2> CR2; /*!< TIM control register 2, Address offset: 0x04 */
34-
TimerRegister<SMCR> SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
35-
TimerRegister<DIER> DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
36-
TimerRegister<SR> SR; /*!< TIM status register, Address offset: 0x10 */
37-
TimerRegister<EGR> EGR; /*!< TIM event generation register, Address offset: 0x14 */
38-
TimerRegister<CCMR1> CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
39-
TimerRegister<CCMR2> CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
40-
TimerRegister<CCER> CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
41-
TimerRegister<CNT> CNT; /*!< TIM counter register, Address offset: 0x24 */
42-
TimerRegister<PSC> PSC; /*!< TIM prescaler, Address offset: 0x28 */
43-
TimerRegister<ARR> ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
44-
TimerRegister<RCR> RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
45-
TimerRegister<CCR1> CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
46-
TimerRegister<CCR2> CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
47-
TimerRegister<CCR3> CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
48-
TimerRegister<CCR4> CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
49-
TimerRegister<BDTR> BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
50-
TimerRegister<DCR> DCR; /*!< TIM DMA control register, Address offset: 0x48 */
51-
TimerRegister<DMAR> DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
34+
TimerRegister<Reg_CR1> CR1; /*!< TIM control register 1, Address offset: 0x00 */
35+
TimerRegister<Reg_CR2> CR2; /*!< TIM control register 2, Address offset: 0x04 */
36+
TimerRegister<Reg_SMCR> SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
37+
TimerRegister<Reg_DIER> DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
38+
TimerRegister<Reg_SR> SR; /*!< TIM status register, Address offset: 0x10 */
39+
TimerRegister<Reg_EGR> EGR; /*!< TIM event generation register, Address offset: 0x14 */
40+
TimerRegister<Reg_CCMR1> CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
41+
TimerRegister<Reg_CCMR2> CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
42+
TimerRegister<Reg_CCER> CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
43+
TimerRegister<Reg_CNT> CNT; /*!< TIM counter register, Address offset: 0x24 */
44+
TimerRegister<Reg_PSC> PSC; /*!< TIM prescaler, Address offset: 0x28 */
45+
TimerRegister<Reg_ARR> ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
46+
TimerRegister<Reg_RCR> RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
47+
TimerRegister<Reg_CCR1> CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
48+
TimerRegister<Reg_CCR2> CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
49+
TimerRegister<Reg_CCR3> CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
50+
TimerRegister<Reg_CCR4> CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
51+
TimerRegister<Reg_BDTR> BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
52+
TimerRegister<Reg_DCR> DCR; /*!< TIM DMA control register, Address offset: 0x48 */
53+
TimerRegister<Reg_DMAR> DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
5254
uint32_t RESERVED1; /*!< Reserved, 0x50 */
53-
TimerRegister<CCMR3> CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
54-
TimerRegister<CCR5> CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
55-
TimerRegister<CCR6> CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
56-
TimerRegister<AF1> AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
57-
TimerRegister<AF2> AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
58-
TimerRegister<TISEL> TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
55+
TimerRegister<Reg_CCMR3> CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
56+
TimerRegister<Reg_CCR5> CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
57+
TimerRegister<Reg_CCR6> CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
58+
TimerRegister<Reg_AF1> AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
59+
TimerRegister<Reg_AF2> AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
60+
TimerRegister<Reg_TISEL> TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
5961
// ========================================================================
6062
// Internal Hardware State (Shadow Registers & Hidden Counters)
6163
// ========================================================================
@@ -103,7 +105,7 @@ class TIM_TypeDef{
103105
return true;
104106
}
105107
};
106-
static_assert(sizeof(TimerRegister<CNT>) == sizeof(uint32_t));
108+
static_assert(sizeof(TimerRegister<Reg_CNT>) == sizeof(uint32_t));
107109
void simulate_ticks(TIM_TypeDef* tim);
108110

109111
template<>

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