Refactor/mpu manager

Inc/HALAL/HALAL.hpp

@@ -37,6 +37,7 @@
 #include "HALAL/Services/FMAC/FMAC.hpp"
 
 #include "HALAL/Models/MPUManager/MPUManager.hpp"
+#include "HALAL/Models/MPU.hpp"
 #include "HALAL/Services/InfoWarning/InfoWarning.hpp"
 #include "HALAL/Services/Watchdog/Watchdog.hpp"
 

Inc/HALAL/Models/MPUManager/MPUManager.hpp

@@ -5,75 +5,8 @@
 
 #define NO_CACHED_RAM_MAXIMUM_SPACE 2048
 
-extern unsigned long _no_cached_ram_start;
-
-
 class MPUManager{
 public:
-	static struct config{
-		bool using_cache = true;
-	}MPUConfig;/**< MPU configuration defined un Runes.hpp*/
-
-	static void start(){
-		MPU_Region_InitTypeDef MPU_InitStruct = {0};
-		HAL_MPU_Disable();
-
-		MPU_InitStruct.Enable = MPU_REGION_ENABLE;
-		MPU_InitStruct.Number = MPU_REGION_NUMBER0;
-		MPU_InitStruct.BaseAddress = 0x0;
-		MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
-		MPU_InitStruct.SubRegionDisable = 0x87;
-		MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
-		MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
-		MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
-		MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
-		MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
-		MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
-		HAL_MPU_ConfigRegion(&MPU_InitStruct);
-		/** Initializes and configures the Region and the memory to be protected
-		*/
-		MPU_InitStruct.Number = MPU_REGION_NUMBER1;
-		MPU_InitStruct.BaseAddress = 0x30000000;
-		MPU_InitStruct.Size = MPU_REGION_SIZE_32KB;
-		MPU_InitStruct.SubRegionDisable = 0x0;
-		MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
-		MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
-		MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
-		HAL_MPU_ConfigRegion(&MPU_InitStruct);
-		/** Initializes and configures the Region and the memory to be protected
-		*/
-		MPU_InitStruct.Number = MPU_REGION_NUMBER2;
-		MPU_InitStruct.Size = MPU_REGION_SIZE_512B;
-		MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
-		MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
-		MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
-		HAL_MPU_ConfigRegion(&MPU_InitStruct);
-		/** Initializes and configures the Region and the memory to be protected
-		*/
-		MPU_InitStruct.Number = MPU_REGION_NUMBER3;
-		MPU_InitStruct.BaseAddress = 0x08000000;
-		MPU_InitStruct.Size = MPU_REGION_SIZE_1MB;
-		MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
-		MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
-		HAL_MPU_ConfigRegion(&MPU_InitStruct);
-
-		MPU_InitStruct.Number = MPU_REGION_NUMBER4;
-		MPU_InitStruct.BaseAddress = 0x38000000;
-		MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
-		MPU_InitStruct.SubRegionDisable = 0x0;
-		MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
-		MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
-		MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
-		HAL_MPU_ConfigRegion(&MPU_InitStruct);
-		/* Enables the MPU */
-		HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
-
-		if(MPUConfig.using_cache){
-			SCB_EnableICache();
-			SCB_EnableDCache();
-		}
-	}
-
 	static void* allocate_non_cached_memory(uint32_t size){
 		void* buffer = (void*)((uint8_t*)no_cached_ram_start + no_cached_ram_occupied_bytes);
 		no_cached_ram_occupied_bytes = no_cached_ram_occupied_bytes + size;

Inc/HALAL/Services/Communication/Ethernet/Ethernet.hpp

@@ -38,7 +38,6 @@ class Ethernet{
 	static void update();
 
 private:
-	static void mpu_start();
 };
 
 #endif

Inc/ST-LIB.hpp

@@ -83,7 +83,7 @@ template <typename... Domains> struct BuildCtx {
   }
 };
 
-using DomainsCtx = BuildCtx<GPIODomain, TimerDomain,
+using DomainsCtx = BuildCtx<MPUDomain, GPIODomain, TimerDomain,
                             DigitalOutputDomain,
                             DigitalInputDomain /*, ADCDomain, PWMDomain, ...*/>;
 
@@ -105,13 +105,15 @@ template <auto &...devs> struct Board {
     constexpr std::size_t timN = domain_size<TimerDomain>();
     constexpr std::size_t doutN = domain_size<DigitalOutputDomain>();
     constexpr std::size_t dinN = domain_size<DigitalInputDomain>();
+    constexpr std::size_t mpuN = domain_size<MPUDomain>();
     // ...
 
     struct ConfigBundle {
       std::array<GPIODomain::Config, gpioN> gpio_cfgs;
       std::array<TimerDomain::Config, timN> tim_cfgs;
       std::array<DigitalOutputDomain::Config, doutN> dout_cfgs;
       std::array<DigitalInputDomain::Config, dinN> din_cfgs;
+      std::array<MPUDomain::Config, mpuN> mpu_cfgs;
       // ...
     };
 
@@ -124,6 +126,8 @@ template <auto &...devs> struct Board {
             ctx.template span<DigitalOutputDomain>()),
         .din_cfgs = DigitalInputDomain::template build<dinN>(
             ctx.template span<DigitalInputDomain>()),
+        .mpu_cfgs = MPUDomain::template build<mpuN>(
+            ctx.template span<MPUDomain>())
         // ...
     };
   }
@@ -135,6 +139,7 @@ template <auto &...devs> struct Board {
     constexpr std::size_t timN = domain_size<TimerDomain>();
     constexpr std::size_t doutN = domain_size<DigitalOutputDomain>();
     constexpr std::size_t dinN = domain_size<DigitalInputDomain>();
+    constexpr std::size_t mpuN = domain_size<MPUDomain>();
     // ...
 
     GPIODomain::Init<gpioN>::init(cfg.gpio_cfgs);
@@ -143,6 +148,7 @@ template <auto &...devs> struct Board {
                                            GPIODomain::Init<gpioN>::instances);
     DigitalInputDomain::Init<dinN>::init(cfg.din_cfgs,
                                          GPIODomain::Init<gpioN>::instances);
+    MPUDomain::Init<mpuN, cfg.mpu_cfgs>::init();
     // ...
   }
 
@@ -165,7 +171,12 @@ template <auto &...devs> struct Board {
     constexpr std::size_t idx = owner_index_of<Domain, Target>();
 
     constexpr std::size_t N = domain_size<Domain>();
-    return Domain::template Init<N>::instances[idx];
+
+    if constexpr (std::is_same_v<Domain, MPUDomain>) {
+      return Domain::template Init<N, cfg.mpu_cfgs>::instances[idx];
+    } else {
+      return Domain::template Init<N>::instances[idx];
+    }
   }
 };
 

STM32H723ZGTX_FLASH.ld

@@ -35,8 +35,8 @@
 ENTRY(Reset_Handler)
 
 /* Highest address of the user mode stack */
-_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1);    /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
+_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM/DTCM */
 _Min_Heap_Size = 0x200;      /* required amount of heap  */
 _Min_Stack_Size = 0x400; /* required amount of stack */
 
@@ -54,6 +54,22 @@ MEMORY
 /* Define output sections */
 SECTIONS
 {
+  /* Export Memory Layout Information for MPU Configuration */
+  __itcm_base = ABSOLUTE(ORIGIN(ITCMRAM));
+  __itcm_size = ABSOLUTE(LENGTH(ITCMRAM));
+  __dtcm_base = ABSOLUTE(ORIGIN(DTCMRAM));
+  __dtcm_size = ABSOLUTE(LENGTH(DTCMRAM));
+  __flash_base = ABSOLUTE(ORIGIN(FLASH));
+  __flash_size = ABSOLUTE(LENGTH(FLASH));
+  __ram_d1_base = ABSOLUTE(ORIGIN(RAM_D1));
+  __ram_d1_size = ABSOLUTE(LENGTH(RAM_D1));
+  __ram_d2_base = ABSOLUTE(ORIGIN(RAM_D2));
+  __ram_d2_size = ABSOLUTE(LENGTH(RAM_D2));
+  __ram_d3_base = ABSOLUTE(ORIGIN(RAM_D3));
+  __ram_d3_size = ABSOLUTE(LENGTH(RAM_D3));
+  __peripheral_base = 0x40000000;
+  __peripheral_size = 0x20000000; /* 512MB */
+
   /* The startup code goes first into FLASH */
   .isr_vector :
   {
@@ -118,6 +134,35 @@ SECTIONS
     PROVIDE_HIDDEN (__fini_array_end = .);
   } >FLASH
 
+  /* MPU D1 Non-Cached Section: Placed at start of RAM_D1 for alignment */
+  .mpu_ram_d1_nc :
+  {
+    . = ALIGN(32);
+    __mpu_d1_nc_start = ABSOLUTE(.);
+
+    /* New MPU system buffers */
+    *(.mpu_ram_d1_nc.buffer)
+
+    /* User manual allocations via D1_NC macro */
+    *(.mpu_ram_d1_nc.user)
+
+    /* Ethernet Rx Pool */
+    . = ALIGN(32);
+    *(.Rx_PoolSection)
+  } >RAM_D1
+
+  /* CALCULATE PADDING FOR MPU SUBREGIONS (D1) */
+  _d1_size = SIZEOF(.mpu_ram_d1_nc);
+  /* Find next power of 2 (up to 512KB for 320KB RAM) */
+  _d1_p2 = (1 << LOG2CEIL(MAX(32, _d1_size)));
+  /* Subregion size is RegionSize / 8 */
+  _d1_sub = _d1_p2 / 8;
+  /* Align effective size to the subregion granularity */
+  _d1_pad = (_d1_size + _d1_sub - 1) / _d1_sub * _d1_sub;
+  /* Advance current pointer to reserve this space */
+  . = __mpu_d1_nc_start + _d1_pad;
+  __mpu_d1_nc_end = ABSOLUTE(.);
+
   /* used by the startup to initialize data */
   _sidata = LOADADDR(.data);
 
@@ -128,12 +173,10 @@ SECTIONS
     _sdata = .;        /* create a global symbol at data start */
     *(.data)           /* .data sections */
     *(.data*)          /* .data* sections */
-    *(.RamFunc)        /* .RamFunc sections */
-    *(.RamFunc*)       /* .RamFunc* sections */
 
     . = ALIGN(4);
     _edata = .;        /* define a global symbol at data end */
-  } >RAM_D1 AT> FLASH
+  } >DTCMRAM AT> FLASH
   /*
     this needs to be the last thing in FLASH
     because the preceeding sections are appended after the one preceeding them
@@ -160,15 +203,10 @@ SECTIONS
     *(.bss*)
     *(COMMON)
 
-    /* ETH_CODE: add placement of RX buffer. STM32H72x/H73x has small D2 RAM, so we need to put it there.
-     * (NOLOAD) attribute used for .bss section to avoid linker warning (.bss initialized by startup code)
-     */
-    . = ALIGN(32);
-    *(.Rx_PoolSection)
     . = ALIGN(4);
     _ebss = .;         /* define a global symbol at bss end */
     __bss_end__ = _ebss;
-  } >RAM_D1
+  } >DTCMRAM
 
   /* User_heap_stack section, used to check that there is enough RAM left */
   ._user_heap_stack :
@@ -179,24 +217,74 @@ SECTIONS
     . = . + _Min_Heap_Size;
     . = . + _Min_Stack_Size;
     . = ALIGN(8);
-  } >RAM_D1
+  } >DTCMRAM
 
-  /* ETH_CODE: add placement of DMA descriptors, rest is used by RX_POOL */
-  .lwip_sec (NOLOAD) :
+  /* MPU D2 Non-Cached Section: Contains Ethernet Descriptors and Generic Buffers */
+  .mpu_ram_d2_nc :
   {
-    . = ABSOLUTE(0x30000000);
-    *(.RxDecripSection) 
+    . = ALIGN(32);
+    __mpu_d2_nc_start = ABSOLUTE(.);
 
-    . = ABSOLUTE(0x30000100);
+    /* ETH Descriptors - Must be aligned */
+    *(.RxDecripSection) 
     *(.TxDecripSection)
 
+    /* New MPU system buffers */
+    *(.mpu_ram_d2_nc.buffer)
+
+    /* User manual allocations via D2_NC macro */
+    *(.mpu_ram_d2_nc.user)
+
   } >RAM_D2
- .stlib_no_cache_ram_pool :
+
+  /* CALCULATE PADDING FOR MPU SUBREGIONS (D2) */
+  _d2_size = SIZEOF(.mpu_ram_d2_nc);
+  /* Find next power of 2 (up to 64KB for 32KB RAM to catch overflow logic if needed) */
+  _d2_p2 = (1 << LOG2CEIL(MAX(32, _d2_size)));
+  _d2_sub = _d2_p2 / 8;
+  _d2_pad = (_d2_size + _d2_sub - 1) / _d2_sub * _d2_sub;
+  . = __mpu_d2_nc_start + _d2_pad;
+  __mpu_d2_nc_end = ABSOLUTE(.);
+
+  /* MPU D3 Non-Cached Section */
+  .mpu_ram_d3_nc :
   {
-  	. = ABSOLUTE(0x38000000);
-  	_no_cached_ram_start = .;
-
+    . = ALIGN(32);
+    __mpu_d3_nc_start = ABSOLUTE(.);
+
+    /* New MPU system buffers */
+    *(.mpu_ram_d3_nc.buffer)
+
+    /* Legacy MPUManager allocations */
+    *(.mpu_ram_d3_nc.legacy)
+
+    /* User manual allocations via D3_NC macro */
+    *(.mpu_ram_d3_nc.user)
+
+
   } >RAM_D3
+
+  /* CALCULATE PADDING FOR MPU SUBREGIONS (D3) */
+  _d3_size = SIZEOF(.mpu_ram_d3_nc);
+  /* Find next power of 2 (up to 32KB for 16KB RAM) */
+  _d3_p2 = (1 << LOG2CEIL(MAX(32, _d3_size)));
+  _d3_sub = _d3_p2 / 8;
+  _d3_pad = (_d3_size + _d3_sub - 1) / _d3_sub * _d3_sub;
+  . = __mpu_d3_nc_start + _d3_pad;
+  __mpu_d3_nc_end = ABSOLUTE(.);
+
+  /* Code running in ITCM RAM (0 Wait States, Instruction Bus) */
+  .ram_code :
+  {
+  	. = ALIGN(4);
+  	_sram_code = .; 
+    *(.ram_code)
+    *(.ram_code*)
+    . = ALIGN(4);
+    _eram_code = .;
+  } >ITCMRAM AT> FLASH
+  _siram_code = LOADADDR(.ram_code);
+
   /* Remove information from the standard libraries */
   /DISCARD/ :
   {
@@ -206,4 +294,40 @@ SECTIONS
   }
 
   .ARM.attributes 0 : { *(.ARM.attributes) }
+
+  /* MPU D1 Cached Section */
+  .ram_d1 :
+  {
+    . = ALIGN(32);
+
+    /* User manual allocations via D1_C macro */
+    *(.ram_d1.user)
+
+    /* New MPU system buffers */
+    *(.ram_d1.buffer)
+  } >RAM_D1
+
+  /* MPU D2 Cached Section */
+  .ram_d2 :
+  {
+    . = ALIGN(32);
+
+    /* User manual allocations via D2_C macro */
+    *(.ram_d2.user)
+
+    /* New MPU system buffers */
+    *(.ram_d2.buffer)
+  } >RAM_D2
+
+  /* MPU D3 Cached Section */
+  .ram_d3 :
+  {
+    . = ALIGN(32);
+
+    /* User manual allocations via D3_C macro */
+    *(.ram_d3.user)
+
+    /* New MPU system buffers */
+    *(.ram_d3.buffer)
+  } >RAM_D3
 }