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nishant-sachdevanishant-sachdeva
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opt checkpoint
1 parent 28b8c8a commit 47549ce

2 files changed

Lines changed: 76 additions & 37 deletions

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‎src/FlowAware.cpp‎

Lines changed: 57 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -30,11 +30,46 @@
3030
#include <algorithm> // for transform
3131

3232
#include <functional>
33+
#include <iostream>
3334
#include <regex>
35+
#include <stack>
3436

3537
using namespace llvm;
3638
using namespace IR2Vec;
3739

40+
// void IR2Vec_FA::getTransitiveUse(
41+
// const Instruction *root, const Instruction *def,
42+
// SmallVector<const Instruction *, 100> &visitedList)
43+
// {
44+
// std::stack<const Instruction *> stack; // Explicit stack for DFS
45+
// stack.push(def);
46+
47+
// while (!stack.empty()) {
48+
// const Instruction *currentDef = stack.top();
49+
// stack.pop();
50+
51+
// visitedList.push_back(currentDef);
52+
// unsigned operandNum = 0;
53+
// for (auto U : currentDef->users()) {
54+
// if (auto use = dyn_cast<Instruction>(U))
55+
// {
56+
// if (std::find(visitedList.begin(), visitedList.end(), use) ==
57+
// visitedList.end())
58+
// {
59+
// if (isMemOp(use->getOpcodeName(), operandNum, memWriteOp) &&
60+
// use->getOperand(operandNum) == currentDef)
61+
// {
62+
// writeDefsMap[root].push_back(use);
63+
// } else if (isMemOp(use->getOpcodeName(), operandNum,
64+
// memAccessOp) && use->getOperand(operandNum) == currentDef) {
65+
// stack.push(use); // Push the next node to the stack
66+
// }
67+
// }
68+
// }
69+
// }
70+
// }
71+
// }
72+
3873
void IR2Vec_FA::getTransitiveUse(
3974
const Instruction *root, const Instruction *def,
4075
SmallVector<const Instruction *, 100> &visitedList) {
@@ -49,10 +84,10 @@ void IR2Vec_FA::getTransitiveUse(
4984
def->print(outs(), true); outs() << "\n";);
5085
IR2VEC_DEBUG(outs() << "Use " << /* use << */ " ";
5186
use->print(outs(), true); outs() << "\n";);
52-
if (isMemOp(use->getOpcodeName(), operandNum, memWriteOps) &&
87+
if (isMemOp(use->getOpcodeName(), operandNum, memWriteOp) &&
5388
use->getOperand(operandNum) == def) {
5489
writeDefsMap[root].push_back(use);
55-
} else if (isMemOp(use->getOpcodeName(), operandNum, memAccessOps) &&
90+
} else if (isMemOp(use->getOpcodeName(), operandNum, memAccessOp) &&
5691
use->getOperand(operandNum) == def) {
5792
getTransitiveUse(root, use, visitedList);
5893
}
@@ -70,8 +105,8 @@ void IR2Vec_FA::collectWriteDefsMap(Module &M) {
70105
for (auto &BB : F) {
71106
for (auto &I : BB) {
72107
unsigned operandNum = 0;
73-
if ((isMemOp(I.getOpcodeName(), operandNum, memAccessOps) ||
74-
isMemOp(I.getOpcodeName(), operandNum, memWriteOps) ||
108+
if ((isMemOp(I.getOpcodeName(), operandNum, memAccessOp) ||
109+
isMemOp(I.getOpcodeName(), operandNum, memWriteOp) ||
75110
strcmp(I.getOpcodeName(), "alloca") == 0) &&
76111
std::find(visitedList.begin(), visitedList.end(), &I) ==
77112
visitedList.end()) {
@@ -294,7 +329,7 @@ void IR2Vec_FA::TransitiveReads(SmallVector<Instruction *, 16> &Killlist,
294329
Instruction *Inst, BasicBlock *ParentBB) {
295330
assert(Inst != nullptr);
296331
unsigned operandNum;
297-
bool isMemAccess = isMemOp(Inst->getOpcodeName(), operandNum, memAccessOps);
332+
bool isMemAccess = isMemOp(Inst->getOpcodeName(), operandNum, memAccessOp);
298333

299334
if (!isMemAccess)
300335
return;
@@ -316,7 +351,7 @@ void IR2Vec_FA::createKilllist(SmallVector<Instruction *, 16> &KillList,
316351

317352
for (User *U : Arg->users()) {
318353
if (Instruction *UseInst = dyn_cast<Instruction>(U)) {
319-
if (isMemOp(UseInst->getOpcodeName(), opnum, memWriteOps)) {
354+
if (isMemOp(UseInst->getOpcodeName(), opnum, memWriteOp)) {
320355
Instruction *OpInst = dyn_cast<Instruction>(UseInst->getOperand(opnum));
321356
if (OpInst && OpInst == Arg)
322357
tempList.push_back(UseInst);
@@ -357,7 +392,7 @@ Vector IR2Vec_FA::func2Vec(Function &F,
357392
for (auto &I : *b) {
358393
unsigned opnum;
359394
SmallVector<Instruction *, 16> lists;
360-
if (isMemOp(I.getOpcodeName(), opnum, memWriteOps) &&
395+
if (isMemOp(I.getOpcodeName(), opnum, memWriteOp) &&
361396
dyn_cast<Instruction>(I.getOperand(opnum))) {
362397
Instruction *argI = cast<Instruction>(I.getOperand(opnum));
363398
createKilllist(lists, argI, &I);
@@ -809,23 +844,22 @@ void IR2Vec_FA::getReachingDefs(llvm::SmallVector<const Instruction *, 10> &RD,
809844
refBBInstMap[i]->print(outs()); outs() << "\n");
810845
}
811846
}
812-
IR2VEC_DEBUG(
813-
outs() << "****************************\n";
814-
outs() << "Reaching defn for "; I->print(outs()); outs() << "\n";
815-
for (auto i
816-
: RD) i->print(outs());
817-
outs() << "\n";
818-
outs()
819-
<< "Call to getReachingDefs Ended****************************\n");
820847
return;
821848
}
822849

823850
llvm_unreachable("unreachable");
824851
return;
825852
}
826853

827-
bool IR2Vec_FA::isMemOp(StringRef opcode, unsigned &operand,
828-
SmallDenseMap<StringRef, unsigned> map) {
854+
bool IR2Vec_FA::isMemOp(StringRef opcode, unsigned &operand, memOpType op) {
855+
856+
auto map =
857+
(op == memAccessOp)
858+
? memAccessOps
859+
: (op == memWriteOp)
860+
? memWriteOps
861+
: throw std::invalid_argument("Invalid MemoryOperation type");
862+
829863
bool isMemOperand = false;
830864
auto It = map.find(opcode);
831865
if (It != map.end()) {
@@ -1119,7 +1153,7 @@ void IR2Vec_FA::solveSingleComponent(
11191153
instVector = partialInstValMap[&I];
11201154

11211155
unsigned operandNum;
1122-
bool isMemWrite = isMemOp(opcodeName, operandNum, memWriteOps);
1156+
bool isMemWrite = isMemOp(opcodeName, operandNum, memWriteOp);
11231157
bool isCyclic = false;
11241158
Vector VecArgs(DIM, 0);
11251159

@@ -1279,7 +1313,7 @@ void IR2Vec_FA::inst2Vec(
12791313
partialInstValMap[&I] = instVector;
12801314

12811315
unsigned operandNum;
1282-
bool isMemWrite = isMemOp(opcodeName, operandNum, memWriteOps);
1316+
bool isMemWrite = isMemOp(opcodeName, operandNum, memWriteOp);
12831317
bool isCyclic = false;
12841318
Vector VecArgs(DIM, 0);
12851319

@@ -1329,13 +1363,10 @@ void IR2Vec_FA::inst2Vec(
13291363
if (!RDList.empty()) {
13301364
for (auto i : RDList) {
13311365
// Check if value of RD is precomputed
1332-
if (instVecMap.find(i) == instVecMap.end()) {
1333-
assert(instVecMap.find(i) != instVecMap.end() &&
1334-
"All RDs should have been solved by Topo Order!");
1335-
} else {
1336-
std::transform(instVecMap[i].begin(), instVecMap[i].end(),
1337-
vecInst.begin(), vecInst.begin(), std::plus<double>());
1338-
}
1366+
assert(instVecMap.find(i) != instVecMap.end() &&
1367+
"All RDs should have been solved by Topo Order!");
1368+
std::transform(instVecMap[i].begin(), instVecMap[i].end(),
1369+
vecInst.begin(), vecInst.begin(), std::plus<double>());
13391370
}
13401371
}
13411372

‎src/include/FlowAware.h‎

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,12 @@ class IR2Vec_FA {
3333
unsigned cyclicCounter;
3434

3535
llvm::SmallDenseMap<llvm::StringRef, unsigned> memWriteOps;
36-
llvm::SmallDenseMap<const llvm::Instruction *, bool> livelinessMap;
3736
llvm::SmallDenseMap<llvm::StringRef, unsigned> memAccessOps;
37+
enum memOpType {
38+
memAccessOp, // Enum field for memory access operations
39+
memWriteOp // Enum field for memory write operations
40+
};
41+
llvm::SmallDenseMap<const llvm::Instruction *, bool> livelinessMap;
3842

3943
llvm::SmallMapVector<const llvm::Instruction *, IR2Vec::Vector, 128>
4044
instVecMap;
@@ -111,9 +115,7 @@ class IR2Vec_FA {
111115
IR2Vec::Vector func2Vec(llvm::Function &F,
112116
llvm::SmallVector<llvm::Function *, 15> &funcStack);
113117

114-
bool isMemOp(llvm::StringRef opcode, unsigned &operand,
115-
llvm::SmallDenseMap<llvm::StringRef, unsigned> map);
116-
std::string splitAndPipeFunctionName(std::string s);
118+
bool isMemOp(llvm::StringRef opcode, unsigned &operand, memOpType op);
117119

118120
void TransitiveReads(llvm::SmallVector<llvm::Instruction *, 16> &Killlist,
119121
llvm::Instruction *Inst, llvm::BasicBlock *ParentBB);
@@ -136,21 +138,27 @@ class IR2Vec_FA {
136138
pgmVector = IR2Vec::Vector(DIM, 0);
137139
res = "";
138140

139-
memWriteOps.try_emplace("store", 1);
140-
memWriteOps.try_emplace("cmpxchg", 0);
141-
memWriteOps.try_emplace("atomicrmw", 0);
141+
auto memWritePairs = {std::make_pair("store", 1),
142+
std::make_pair("cmpxchg", 0),
143+
std::make_pair("atomicrmw", 0)};
144+
145+
// Insert the pairs using insert with a range
146+
memWriteOps.insert(memWritePairs.begin(), memWritePairs.end());
147+
148+
auto memAccessPairs = {std::make_pair("getelementptr", 0),
149+
std::make_pair("load", 0)};
142150

143-
memAccessOps.try_emplace("getelementptr", 0);
144-
memAccessOps.try_emplace("load", 0);
151+
memAccessOps.insert(memAccessPairs.begin(), memAccessPairs.end());
145152

146153
dataMissCounter = 0;
147154
cyclicCounter = 0;
148155

149156
collectWriteDefsMap(M);
150157

151-
llvm::CallGraph cg = llvm::CallGraph(M);
158+
llvm::CallGraph callGraph = llvm::CallGraph(M);
152159

153-
for (auto callItr = cg.begin(); callItr != cg.end(); callItr++) {
160+
for (auto callItr = callGraph.begin(); callItr != callGraph.end();
161+
callItr++) {
154162
if (callItr->first && !callItr->first->isDeclaration()) {
155163
auto ParentFunc = callItr->first;
156164
llvm::CallGraphNode *cgn = callItr->second.get();

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