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iOS: Compile EI/ERET as block terminators and live-cycle COP0 Count/PERF
Port the COP0 block-terminator and live-cycle handling from the mac arm64 backend (upstream 673135b) so EI/ERET and the MFC0/MTC0 Count/PERF polls no longer force an interpreter single-step block. EI (enable interrupts) and ERET (exception return) are now compiled as in-block terminators matching x86 recEI/recERET: run the interpreter handler inline (Interp::EI sets Status.EIE; Interp::ERET writes cpuRegs.pc), then end the block so the tail event-tests and dispatches from cpuRegs.pc. This keeps the preceding straight-line ops in the same block and lets the block's cycles ride forward to the post-loop commit instead of fragmenting the block around every EI/ERET. MFC0/MTC0 of Count(rd9)/PERF(rd25) commit the block's accumulated cycles before an inline interpreter call (so the read sees a live cpuRegs.cycle) rather than single-stepping. Games busy-poll Count for timing and these were ~80% of Jackie Chan Adventures' EE fallbacks; the per-op commit also fixes the stale-value hazard where two Count reads in one block returned the same value. Correctness is inherited from the interpreter handlers; no native COP0 emitter is needed. Both paths are inserted in recRecompile before the recTranslateOpOptimized straight-line fallback.
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‎app/src/main/cpp/pcsx2/arm64/aR5900.cpp‎

Lines changed: 94 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3058,6 +3058,24 @@ static bool recIsCop0DI(u32 op)
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return (op >> 26) == 0x10 && ((op >> 21) & 0x1f) == 0x10 && (op & 0x3f) == 0x39;
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}
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// COP0 EI (enable interrupts, funct 0x38) / ERET (exception return, funct 0x18) —
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// CO ops (rs==0x10). x86 compiles both via recBranchCall: end the block, run the
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// interpreter handler, then event-test + dispatch (EI so a now-unmasked pending IRQ
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// is serviced; ERET because it writes cpuRegs.pc). recRecompile handles them that way
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// instead of single-stepping (the top EE interpreter fallback after the BC0/MADD work).
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static bool recIsCop0EI(u32 op)
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{
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return (op >> 26) == 0x10 && ((op >> 21) & 0x1f) == 0x10 && (op & 0x3f) == 0x38;
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}
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static bool recIsCop0ERET(u32 op)
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{
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return (op >> 26) == 0x10 && ((op >> 21) & 0x1f) == 0x10 && (op & 0x3f) == 0x18;
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}
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static bool recIsCop0EIorERET(u32 op)
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{
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return recIsCop0EI(op) || recIsCop0ERET(op);
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}
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// MIPS trap ops: SPECIAL T{GE,GEU,LT,LTU,EQ,NE} (funct 0x30-0x34,0x36) and REGIMM
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// T{GE,GEU,LT,LTU,EQ,NE}I (rt 0x08-0x0C,0x0E). Emitted natively (block-conditional)
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// in recRecompile — see recEmitTrapCompareIfTrap.
@@ -3532,6 +3550,26 @@ static bool recOpNeedsCycleFlush(u32 op)
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return (op >> 26) == OP_LQC2 || (op >> 26) == OP_SQC2;
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}
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// True for MFC0/MTC0 of the Count (rd 9) or PERF (rd 25) registers — the COP0 ops the EE
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// rec previously single-stepped (recTranslateOpOptimized returns false for them) because
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// they read a live cpuRegs.cycle this rec only flushes at the block tail. Games busy-poll
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// Count for timing, so the single-step path can dominate EE (Jackie Chan Adventures: ~80%
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// of EE fallbacks). recRecompile handles these by committing the block's accumulated cycles
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// before an INLINE interp call (so the read is live), instead of the expensive single-step.
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// Per-op commit also fixes the historic "two MFC0 Count in one block read the same stale
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// value -> games lock up" hazard: each read now advances cpuRegs.cycle. Excludes BC0 / ERET
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// / EI / DI / WAIT, which still single-step (they write PC or gate interrupts).
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static bool recCop0NeedsLiveCycle(u32 op)
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{
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if ((op >> 26) != 0x10)
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return false; // COP0
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const u32 rs = (op >> 21) & 0x1f;
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if (rs != 0x00 && rs != 0x04)
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return false; // MFC0 / MTC0 only (BC0 rs==0x08 + C0 rs==0x10 keep their paths)
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const u32 rd = (op >> 11) & 0x1f;
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return (rd == 9 || rd == 25); // Count / PERF
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}
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// CALLMS (COP2 SPECIAL1 funct 0x38) / CALLMSR (0x39) — x86's only INTERPRETATE_COP2_FUNC ops
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// (microVU_Macro.inl:295-296). M5.5 keeps them on the inline interpreter (faithful: the interp
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// path self-finishes VU0 and launches the microprogram via vu0ExecMicro), but unlike the native
@@ -4732,6 +4770,62 @@ static void recRecompile(u32 startpc)
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raw_cycles = 0;
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}
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// MFC0/MTC0 of Count(rd9)/PERF(rd25): commit the block's cycles (incl. this op) so
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// the read is live, clear the accumulator, then INLINE-interp in-block — instead of
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// the expensive single-step path (these were ~80% of Jackie Chan's EE fallbacks, a
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// Count busy-poll). Same commit-then-inline shape as the CALLMS launch above; the
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// per-op commit makes consecutive Count reads see an advancing cpuRegs.cycle (no
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// stale-value lock-up). See recCop0NeedsLiveCycle.
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if (recCop0NeedsLiveCycle(op))
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{
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raw_cycles += eeOpCycles(op);
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recEmitCommitBlockCycles(raw_cycles);
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raw_cycles = 0;
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// Flush + kill the GPR register cache / const tracking before the inline interp,
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// exactly like the trap path: MTC0 reads cpuRegs.GPR.r[rt] from memory (must be
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// authoritative) and MFC0 WRITES it — a stale cached copy in a callee-saved host
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// reg would survive the C call and shadow the Count value, silently breaking the
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// very poll loop this targets.
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recCacheFlushAll(cache_state);
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recCacheKillAll(cache_state);
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recConstKillAll(const_state);
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recEmitInterpInline(op);
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waitloop_possible = false; // inline live-cycle op — not a wait-loop body
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pc += 4;
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endpc = pc;
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if (++compiled >= MAX_BLOCK_INSTS)
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{
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recEmitWritePc(pc);
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known_dispatch_pc = true;
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dispatch_pc = pc;
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break;
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}
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continue;
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}
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// COP0 EI / ERET (CO ops, rs==0x10; funct 0x38 / 0x18). Faithful to x86
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// recEI/recERET (recBranchCall): run the interpreter handler in-block, then END
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// the block so the tail event-tests + dispatches from cpuRegs.pc. EI: a now-
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// unmasked pending IRQ gets serviced by that event test (x86 "must branch after
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// enabling interrupts"); ERET: it writes cpuRegs.pc, so the dispatch must read it.
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// Like the handled-branch path, the block's cycles ride in raw_cycles and the
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// post-loop commits them — no early commit, so no spurious tail +1. Replaces the
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// per-op single-step (the top EE interpreter fallback after the BC0/MADD work).
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if (recIsCop0EIorERET(op))
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{
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raw_cycles += eeOpCycles(op);
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recCacheFlushAll(cache_state);
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recCacheKillAll(cache_state);
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recConstKillAll(const_state);
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if (!recIsCop0ERET(op))
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recEmitWritePc(pc + 4); // EI doesn't write PC; resume after it unless the event test diverts
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recEmitInterpInline(op); // Interp::EI sets Status.EIE / Interp::ERET sets cpuRegs.pc
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waitloop_possible = false;
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known_dispatch_pc = false; // dispatch from cpuRegs.pc: an IRQ raised by the tail event test, or ERET's new pc
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endpc = pc + 4;
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break;
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}
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// Straight-line op we can codegen? (Generators decode from `op` directly;
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// they never read cpuRegs.code, so nothing to set here at compile time.)
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if (recTranslateOpOptimized(op, const_state, cache_state))

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