My project final.v

/**
 * This is an autogenerated netlist code from CircuitVerse. Verilog Code can be
 * tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. This is an
 * experimental module and some manual changes make need to be done in order for
 * this to work.
 *
 * If you have any ideas/suggestions or bug fixes, raise an issue
 * on https://github.com/CircuitVerse/CircuitVerse/issues/new/choose
 */

/*
  Element Usage Report
    Button - 2 times
    AndGate - 25 times
    DflipFlop - 2 times
    OrGate - 5 times
    TflipFlop - 13 times
    XorGate - 8 times
    NotGate - 15 times
    DigitalLed - 4 times
    Splitter - 1 times
    SixteenSegDisplay - 9 times
    Input - 23 times
    Multiplexer - 3 times
    Demultiplexer - 3 times
    PriorityEncoder - 1 times
*/

/*
  Usage Instructions and Tips
    Labels - Ensure unique label names and avoid using verilog keywords
    Warnings - Connect all optional inputs to remove warnings
    Button - Buttons are not natively supported in verilog, consider using Inputs instead
*/

// Sample Testbench Code - Uncomment to use

/*
module TestBench();

  reg inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8, inp_9, inp_10, inp_11, inp_12, inp_13;
  reg [15:0] inp_14, inp_15, inp_16, inp_17, inp_18, inp_19, inp_20, inp_21, inp_22;


  Main DUT0(inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8, inp_9, inp_10, inp_11, inp_12, inp_13, inp_14, inp_15, inp_16, inp_17, inp_18, inp_19, inp_20, inp_21, inp_22);

  initial begin
    inp_0 = 0;
    inp_1 = 0;
    inp_2 = 0;
    inp_3 = 0;
    inp_4 = 0;
    inp_5 = 0;
    inp_6 = 0;
    inp_7 = 0;
    inp_8 = 0;
    inp_9 = 0;
    inp_10 = 0;
    inp_11 = 0;
    inp_12 = 0;
    inp_13 = 0;
    inp_14 = 0;
    inp_15 = 0;
    inp_16 = 0;
    inp_17 = 0;
    inp_18 = 0;
    inp_19 = 0;
    inp_20 = 0;
    inp_21 = 0;
    inp_22 = 0;

    #15

    #10

    $finish;

  end
endmodule

*/

module Main(inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8, inp_9, inp_10, inp_11, inp_12, inp_13, inp_14, inp_15, inp_16, inp_17, inp_18, inp_19, inp_20, inp_21, inp_22);
  input inp_0, inp_1, inp_2, inp_3, inp_4, inp_5, inp_6, inp_7, inp_8, inp_9, inp_10, inp_11, inp_12, inp_13;
  input [15:0] inp_14, inp_15, inp_16, inp_17, inp_18, inp_19, inp_20, inp_21, inp_22;
  wire Button_1_out, and_7_out, DflipFlop_1_Q, DflipFlop_1_Q_inv, and_6_out, or_4_out, or_3_out, and_5_out, DflipFlop_0_Q, and_2_out, and_3_out, or_2_out, TflipFlop_12_Q, xor_7_out, or_0_out, not_0_out, and_15_out, and_11_out, TflipFlop_10_Q, not_11_out, and_10_out, TflipFlop_11_Q, not_12_out, and_8_out, and_13_out, and_14_out, TflipFlop_8_Q, not_13_out, and_9_out, and_12_out, TflipFlop_9_Q, not_14_out, TflipFlop_4_Q, xor_6_out, TflipFlop_3_Q, xor_5_out, TflipFlop_6_Q, xor_0_out, TflipFlop_5_Q, xor_4_out, TflipFlop_0_Q, xor_2_out, TflipFlop_2_Q, xor_1_out, TflipFlop_1_Q, xor_3_out, and_0_out, or_1_out, not_10_out, TflipFlop_7_Q, and_1_out, not_9_out, Button_0_out, and_4_out, Multiplexer_1_out, Multiplexer_2_out, Demultiplexer_2_out_0, Demultiplexer_2_out_1, Demultiplexer_1_out_0, Demultiplexer_1_out_1, Demultiplexer_0_out_0, Demultiplexer_0_out_1, PriorityEncoder_0_out_0, PriorityEncoder_0_out_1, Multiplexer_0_out, not_7_out, not_6_out, not_5_out, not_2_out, not_8_out, not_1_out, not_4_out, not_3_out;
  wire [15:0] Splitter_0_cmb, and_24_out, and_23_out, and_22_out, and_21_out, and_19_out, and_18_out, and_20_out, and_17_out, and_16_out;
  Button0 Button_1(Button_1_out);
  assign and_7_out = Button_1_out & and_1_out;
  DflipFlop DflipFlop_1(DflipFlop_1_Q, DflipFlop_1_Q_inv, and_7_out, and_8_out, Button_0_out, , );
  assign and_6_out = Demultiplexer_0_out_1 & DflipFlop_1_Q_inv;
  assign or_4_out = not_10_out | and_6_out;
  assign or_3_out = Demultiplexer_1_out_0 | or_4_out;
  assign and_5_out = and_1_out & or_3_out;
  DflipFlop DflipFlop_0(DflipFlop_0_Q, , and_5_out, not_0_out, , , );
  assign and_2_out = DflipFlop_0_Q & Button_0_out;
  assign and_3_out = Demultiplexer_0_out_1 & and_2_out;
  assign or_2_out = and_4_out | and_3_out;
  TflipFlop TflipFlop_12(TflipFlop_12_Q, , and_5_out, not_8_out, or_2_out, or_2_out, or_1_out);
  assign xor_7_out = inp_3 ^ TflipFlop_12_Q;
  assign or_0_out = xor_1_out | xor_2_out | xor_3_out | xor_4_out | xor_0_out | xor_5_out | xor_6_out | xor_7_out;
  assign not_0_out = ~or_0_out;
  assign and_15_out = Demultiplexer_0_out_1 & DflipFlop_1_Q & not_0_out;
  assign and_11_out = and_10_out & and_15_out;
  
      always @ (*)
        $display("DigitalLed:and_11_out=%d", and_11_out);
  TflipFlop TflipFlop_10(TflipFlop_10_Q, , and_15_out, inp_13, , , );
  assign not_11_out = ~TflipFlop_10_Q;
  assign and_10_out = not_11_out & not_12_out;
  TflipFlop TflipFlop_11(TflipFlop_11_Q, , TflipFlop_10_Q, inp_13, , , );
  assign not_12_out = ~TflipFlop_11_Q;
  assign and_8_out = not_0_out & Demultiplexer_0_out_1;
  assign and_13_out = not_0_out & Demultiplexer_1_out_1;
  assign and_14_out = Demultiplexer_1_out_1 & and_13_out;
  assign Splitter_0_cmb = {and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out,and_14_out};
  assign and_24_out = inp_21 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_24_out,} = {%16b,%1b}", and_24_out, );
  assign and_23_out = inp_22 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_23_out,} = {%16b,%1b}", and_23_out, );
  assign and_22_out = inp_20 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_22_out,} = {%16b,%1b}", and_22_out, );
  assign and_21_out = inp_19 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_21_out,} = {%16b,%1b}", and_21_out, );
  assign and_19_out = inp_18 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_19_out,} = {%16b,%1b}", and_19_out, );
  assign and_18_out = inp_17 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_18_out,} = {%16b,%1b}", and_18_out, );
  assign and_20_out = inp_16 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_20_out,} = {%16b,%1b}", and_20_out, );
  assign and_17_out = inp_15 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_17_out,} = {%16b,%1b}", and_17_out, );
  assign and_16_out = inp_14 & Splitter_0_cmb;
  
      always @ (*)
        $display("SixteenSegDisplay:{and_16_out,} = {%16b,%1b}", and_16_out, );
  TflipFlop TflipFlop_8(TflipFlop_8_Q, , and_14_out, inp_12, , , );
  assign not_13_out = ~TflipFlop_8_Q;
  assign and_9_out = not_13_out & not_14_out;
  assign and_12_out = Demultiplexer_1_out_1 & and_9_out;
  
      always @ (*)
        $display("DigitalLed:and_12_out=%d", and_12_out);
  TflipFlop TflipFlop_9(TflipFlop_9_Q, , TflipFlop_8_Q, inp_12, , , );
  assign not_14_out = ~TflipFlop_9_Q;
  
      always @ (*)
        $display("DigitalLed:and_13_out=%d", and_13_out);
  TflipFlop TflipFlop_4(TflipFlop_4_Q, , and_5_out, not_7_out, or_2_out, or_2_out, or_1_out);
  assign xor_6_out = inp_7 ^ TflipFlop_4_Q;
  TflipFlop TflipFlop_3(TflipFlop_3_Q, , and_5_out, not_6_out, or_2_out, or_2_out, or_1_out);
  assign xor_5_out = inp_6 ^ TflipFlop_3_Q;
  TflipFlop TflipFlop_6(TflipFlop_6_Q, , and_5_out, not_5_out, or_2_out, or_2_out, or_1_out);
  assign xor_0_out = inp_5 ^ TflipFlop_6_Q;
  TflipFlop TflipFlop_5(TflipFlop_5_Q, , and_5_out, not_4_out, or_2_out, or_2_out, or_1_out);
  assign xor_4_out = inp_1 ^ TflipFlop_5_Q;
  TflipFlop TflipFlop_0(TflipFlop_0_Q, , and_5_out, not_2_out, or_2_out, or_2_out, or_1_out);
  assign xor_2_out = inp_4 ^ TflipFlop_0_Q;
  TflipFlop TflipFlop_2(TflipFlop_2_Q, , and_5_out, not_1_out, or_2_out, or_2_out, or_1_out);
  assign xor_1_out = inp_2 ^ TflipFlop_2_Q;
  TflipFlop TflipFlop_1(TflipFlop_1_Q, , and_5_out, not_3_out, or_2_out, or_2_out, or_1_out);
  assign xor_3_out = inp_0 ^ TflipFlop_1_Q;
  assign and_0_out = DflipFlop_0_Q & Demultiplexer_0_out_1;
  assign or_1_out = Demultiplexer_1_out_0 | and_0_out;
  assign not_10_out = ~DflipFlop_1_Q;
  TflipFlop TflipFlop_7(TflipFlop_7_Q, , Button_1_out, not_9_out, , , );
  assign and_1_out = Button_1_out & TflipFlop_7_Q;
  assign not_9_out = ~Button_1_out;
  Button1 Button_0(Button_0_out);
  assign and_4_out = Demultiplexer_1_out_0 & Button_0_out;
  Multiplexer2 Multiplexer_1(Multiplexer_1_out, inp_11, inp_10, PriorityEncoder_0_out_0);
  Multiplexer2 Multiplexer_2(Multiplexer_2_out, Multiplexer_0_out, Multiplexer_1_out, PriorityEncoder_0_out_1);
  Demultiplexer2 Demultiplexer_2(Demultiplexer_2_out_0, Demultiplexer_2_out_1, Multiplexer_2_out, PriorityEncoder_0_out_0);
  Demultiplexer2 Demultiplexer_1(Demultiplexer_1_out_0, Demultiplexer_1_out_1, Demultiplexer_2_out_1, PriorityEncoder_0_out_1);
  Demultiplexer2 Demultiplexer_0(Demultiplexer_0_out_0, Demultiplexer_0_out_1, Demultiplexer_2_out_0, PriorityEncoder_0_out_1);
  
      always @ (*)
        $display("DigitalLed:Demultiplexer_0_out_0=%d", Demultiplexer_0_out_0);
  PriorityEncoder4 #(2) PriorityEncoder_0(PriorityEncoder_0_out_0, PriorityEncoder_0_out_1, , inp_9, inp_8, inp_11, inp_10);
  Multiplexer2 Multiplexer_0(Multiplexer_0_out, inp_9, inp_8, PriorityEncoder_0_out_0);
  assign not_7_out = ~inp_7;
  assign not_6_out = ~inp_6;
  assign not_5_out = ~inp_5;
  assign not_2_out = ~inp_4;
  assign not_8_out = ~inp_3;
  assign not_1_out = ~inp_2;
  assign not_4_out = ~inp_1;
  assign not_3_out = ~inp_0;
endmodule
// Skeleton for Button0
    /*
    module Button0(out);
      output reg out;
    
      initial begin
        //do something with the button here
      end
    endmodule
    */
    // Skeleton for Button1
    /*
    module Button1(out);
      output reg out;
    
      initial begin
        //do something with the button here
      end
    endmodule
    */
    
module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
    parameter WIDTH = 1;
    output reg [WIDTH-1:0] q, q_inv;
    input clk, a_rst, pre, en;
    input [WIDTH-1:0] d;

    always @ (posedge clk or posedge a_rst)
    if (a_rst) begin
        q <= 'b0;
        q_inv <= 'b1;
    end else if (en == 0) ;
    else begin
        q <= d;
        q_inv <= ~d;
    end
endmodule
    
        module TflipFlop(q, q_inv, clk, t, a_rst, pre, en);
          parameter WIDTH = 1;
          output reg [WIDTH-1:0] q, q_inv;
          input clk, a_rst, pre, en;
          input [WIDTH-1:0] t;
        
          always @ (posedge clk or posedge a_rst)
            if (a_rst) begin
              q <= 'b0;
              q_inv <= 'b1;
            end else if (en == 0) ;
            else if (t) begin
              q <= q ^ t;
              q_inv <= ~q ^ t;
            end
        endmodule
        
module Multiplexer2(out, in0, in1, sel);
  parameter WIDTH = 1;
  output reg [WIDTH-1:0] out;
  input [WIDTH-1:0] in0, in1;
  input [0:0] sel;
  
  always @ (*)
    case (sel)
      0 : out = in0;
      1 : out = in1;
    endcase
endmodule


module Demultiplexer2(out0, out1, in, sel);
  parameter WIDTH = 1;
  output reg [WIDTH-1:0] out0, out1;
  input [WIDTH-1:0] in;
  input [0:0] sel;
  
  always @ (*) begin
    out0 = 0;
    out1 = 0;
    case (sel)
      0 : out0 = in;
      1 : out1 = in;
    endcase
  end
endmodule

module PriorityEncoder4(sel, ze, in0, in1, in2, in3);
  output reg [1:0] sel;
  output reg ze;
  input in0, in1, in2, in3;

  always @ (*) begin
    sel = 0;
    ze = 0;
    if (in3)
      sel = 3;
    else
      ze = 1;
  end
endmodule