Rollup merge of rust-lang#157467 - folkertdev:stdarch-sync-2026-06-05, r=folkertdev

stdarch subtree update

Subtree update of `stdarch` to rust-lang/stdarch@995221d.

Created using https://github.com/rust-lang/josh-sync.

r? @ghost

Author: JonathanBrouwer

library/core/src/lib.rs

@@ -181,6 +181,7 @@
 #![feature(aarch64_unstable_target_feature)]
 #![feature(arm_target_feature)]
 #![feature(avx10_target_feature)]
+#![feature(clflushopt_target_feature)]
 #![feature(hexagon_target_feature)]
 #![feature(loongarch_target_feature)]
 #![feature(mips_target_feature)]

library/stdarch/crates/core_arch/missing-x86.md

@@ -1,41 +1,4 @@
 
-<details><summary>["AMX-BF16"]</summary><p>
-
-  * [ ] [`__tile_dpbf16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbf16ps)
-</p></details>
-
-
-<details><summary>["AMX-COMPLEX"]</summary><p>
-
-  * [ ] [`__tile_cmmimfp16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_cmmimfp16ps)
-  * [ ] [`__tile_cmmrlfp16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_cmmrlfp16ps)
-</p></details>
-
-
-<details><summary>["AMX-FP16"]</summary><p>
-
-  * [ ] [`__tile_dpfp16ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpfp16ps)
-</p></details>
-
-
-<details><summary>["AMX-INT8"]</summary><p>
-
-  * [ ] [`__tile_dpbssd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbssd)
-  * [ ] [`__tile_dpbsud`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbsud)
-  * [ ] [`__tile_dpbusd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbusd)
-  * [ ] [`__tile_dpbuud`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_dpbuud)
-</p></details>
-
-
-<details><summary>["AMX-TILE"]</summary><p>
-
-  * [ ] [`__tile_loadd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_loadd)
-  * [ ] [`__tile_stored`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_stored)
-  * [ ] [`__tile_stream_loadd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_stream_loadd)
-  * [ ] [`__tile_zero`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=__tile_zero)
-</p></details>
-
-
 <details><summary>["AVX512_FP16"]</summary><p>
 
   * [ ] [`_mm256_set1_pch`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_pch)
@@ -70,12 +33,6 @@
 </p></details>
 
 
-<details><summary>["CLFLUSHOPT"]</summary><p>
-
-  * [ ] [`_mm_clflushopt`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clflushopt)
-</p></details>
-
-
 <details><summary>["CLWB"]</summary><p>
 
   * [ ] [`_mm_clwb`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clwb)

library/stdarch/crates/core_arch/src/aarch64/mod.rs

@@ -26,16 +26,16 @@ mod neon;
 pub use self::neon::*;
 
 // The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`.
-#[cfg(any(target_arch = "aarch64", doc))]
+#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))]
 mod sve;
-#[cfg(any(target_arch = "aarch64", doc))]
+#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub use self::sve::*;
 
 // The rest of `core_arch::aarch64` is available on `arm64ec` but SVE is not supported on `arm64ec`.
-#[cfg(any(target_arch = "aarch64", doc))]
+#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))]
 mod sve2;
-#[cfg(any(target_arch = "aarch64", doc))]
+#[cfg(any(all(target_arch = "aarch64", target_endian = "little"), doc))]
 #[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
 pub use self::sve2::*;