riscv: allow single-precision float ABI (lp64f / ilp32f)

The header rejected __riscv_float_abi_single with an #error, but
the F and D extensions share the same FCSR. The hard-float inline
implementations below the guard use only csrr/csrw/csrc on fcsr
and fflags, both of which are present whenever F is present. So
lp64f / ilp32f can use the same code path as the double ABI.

Closes #262.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

Author: ViralBShah

include/openlibm_fenv_riscv.h

@@ -74,13 +74,10 @@ __BEGIN_DECLS
 extern const fenv_t	__fe_dfl_env;
 #define	FE_DFL_ENV	(&__fe_dfl_env)
 
-#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double)
-#if defined(__riscv_float_abi_single)
-#error single precision floating point ABI not supported
-#else
+#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double) && \
+    !defined(__riscv_float_abi_single)
 #error compiler did not set soft/hard float macros
 #endif
-#endif
 
 #ifndef __riscv_float_abi_soft
 #define	__rfs(__fcsr)	__asm __volatile("csrr %0, fcsr" : "=r" (__fcsr))