Fix SQRTSS/SQRTSD semantics

Author: mrexodia

lib/Arch/X86/Semantics/SSE.cpp

@@ -1682,31 +1682,35 @@ IF_AVX(DEF_ISEL(VMOVSHDUP_YMMqq_YMMqq) = MOVSHDUP<VV256W, V256>;)
 
 namespace {
 
-template <typename S1>
-DEF_SEM(SQRTSS, V128W dst, S1 src1) {
+template <typename D, typename S1, typename S2>
+DEF_SEM(SQRTSS, D dst, S1 src1, S2 src2) {
+
+  // Extract a "single-precision" (32-bit) float from [31:0] of src2 vector:
+  auto src_float = FExtractV32(FReadV32(src2), 0);
 
-  // Extract a "single-precision" (32-bit) float from [31:0] of src1 vector:
-  auto src_float = FExtractV32(FReadV32(src1), 0);
+  // Initialize dest vector, while also copying src1[127:32] -> dst[127:32].
+  auto temp_vec = FReadV32(src1);
 
-  // Store the square root result in dest[32:0]:
+  // Store the square root result in dest[31:0]:
   auto square_root = SquareRoot32(memory, state, src_float);
-  auto temp_vec = FReadV32(dst);  // initialize a destination vector
   temp_vec = FInsertV32(temp_vec, 0, square_root);
 
   // Write out the result and return memory state:
   FWriteV32(dst, temp_vec);  // SSE: Writes to XMM, AVX: Zero-extends XMM.
   return memory;
 }
 
-template <typename S1>
-DEF_SEM(RSQRTSS, V128W dst, S1 src1) {
+template <typename D, typename S1, typename S2>
+DEF_SEM(RSQRTSS, D dst, S1 src1, S2 src2) {
 
-  // Extract a "single-precision" (32-bit) float from [31:0] of src1 vector:
-  auto src_float = FExtractV32(FReadV32(src1), 0);
+  // Extract a "single-precision" (32-bit) float from [31:0] of src2 vector:
+  auto src_float = FExtractV32(FReadV32(src2), 0);
 
-  // Store the square root result in dest[32:0]:
+  // Initialize dest vector, while also copying src1[127:32] -> dst[127:32].
+  auto temp_vec = FReadV32(src1);
+
+  // Store the square root result in dest[31:0]:
   auto square_root = SquareRoot32(memory, state, src_float);
-  auto temp_vec = FReadV32(dst);  // initialize a destination vector
   temp_vec = FInsertV32(temp_vec, 0, FDiv(1.0f, square_root));
 
   // Write out the result and return memory state:
@@ -1753,8 +1757,8 @@ DEF_SEM(VRSQRTSS, D dst, S1 src1, S2 src2) {
 #endif  // HAS_FEATURE_AVX
 }  // namespace
 
-DEF_ISEL(SQRTSS_XMMss_MEMss) = SQRTSS<MV32>;
-DEF_ISEL(SQRTSS_XMMss_XMMss) = SQRTSS<V128>;
+DEF_ISEL(SQRTSS_XMMss_MEMss) = SQRTSS<V128W, V128, MV32>;
+DEF_ISEL(SQRTSS_XMMss_XMMss) = SQRTSS<V128W, V128, V128>;
 IF_AVX(DEF_ISEL(VSQRTSS_XMMdq_XMMdq_MEMd) = VSQRTSS<VV128W, V128, MV32>;)
 IF_AVX(DEF_ISEL(VSQRTSS_XMMdq_XMMdq_XMMd) = VSQRTSS<VV128W, V128, V128>;)
 /*
@@ -1763,8 +1767,8 @@ IF_AVX(DEF_ISEL(VSQRTSS_XMMdq_XMMdq_XMMd) = VSQRTSS<VV128W, V128, V128>;)
 4318 VSQRTSS VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512 AVX512EVEX AVX512F_SCALAR ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR
 */
 
-DEF_ISEL(RSQRTSS_XMMss_MEMss) = RSQRTSS<MV32>;
-DEF_ISEL(RSQRTSS_XMMss_XMMss) = RSQRTSS<V128>;
+DEF_ISEL(RSQRTSS_XMMss_MEMss) = RSQRTSS<V128W, V128, MV32>;
+DEF_ISEL(RSQRTSS_XMMss_XMMss) = RSQRTSS<V128W, V128, V128>;
 IF_AVX(DEF_ISEL(VRSQRTSS_XMMdq_XMMdq_MEMd) = VRSQRTSS<VV128W, V128, MV32>;)
 IF_AVX(DEF_ISEL(VRSQRTSS_XMMdq_XMMdq_XMMd) = VRSQRTSS<VV128W, V128, V128>;)
 
@@ -1801,15 +1805,17 @@ DEF_HELPER(SquareRoot64, float64_t src_float)->float64_t {
   return square_root;
 }
 
-template <typename S1>
-DEF_SEM(SQRTSD, V128W dst, S1 src1) {
+template <typename D, typename S1, typename S2>
+DEF_SEM(SQRTSD, D dst, S1 src1, S2 src2) {
+
+  // Extract a "double-precision" (64-bit) float from [63:0] of src2 vector:
+  auto src_float = FExtractV64(FReadV64(src2), 0);
 
-  // Extract a "double-precision" (64-bit) float from [63:0] of src1 vector:
-  auto src_float = FExtractV64(FReadV64(src1), 0);
+  // Initialize dest vector, while also copying src1[127:64] -> dst[127:64].
+  auto temp_vec = FReadV64(src1);
 
   // Store the square root result in dest[63:0]:
   auto square_root = SquareRoot64(memory, state, src_float);
-  auto temp_vec = FReadV64(dst);  // initialize a destination vector
   temp_vec = FInsertV64(temp_vec, 0, square_root);
 
   // Write out the result and return memory state:
@@ -1839,8 +1845,8 @@ DEF_SEM(VSQRTSD, D dst, S1 src1, S2 src2) {
 
 }  // namespace
 
-DEF_ISEL(SQRTSD_XMMsd_MEMsd) = SQRTSD<MV64>;
-DEF_ISEL(SQRTSD_XMMsd_XMMsd) = SQRTSD<V128>;
+DEF_ISEL(SQRTSD_XMMsd_MEMsd) = SQRTSD<V128W, V128, MV64>;
+DEF_ISEL(SQRTSD_XMMsd_XMMsd) = SQRTSD<V128W, V128, V128>;
 IF_AVX(DEF_ISEL(VSQRTSD_XMMdq_XMMdq_MEMq) = VSQRTSD<VV128W, V128, MV64>;)
 IF_AVX(DEF_ISEL(VSQRTSD_XMMdq_XMMdq_XMMq) = VSQRTSD<VV128W, V128, V128>;)
 /*