@@ -358,11 +358,11 @@ llvm::Value *InstructionLifter::LoadWordRegValOrZero(llvm::BasicBlock *block,
358358
359359 CHECK (val_type) << " Register " << reg_name << " expected to be an integer." ;
360360
361- auto val_size = val_type->getBitWidth ();
362- auto word_size = word_type->getBitWidth ();
361+ auto val_size = val_type->getIntegerBitWidth ();
362+ auto word_size = word_type->getIntegerBitWidth ();
363363 CHECK_LE (val_size, word_size)
364364 << " Register " << reg_name << " expected to be no larger than the "
365- << " machine word size (" << word_type->getBitWidth () << " bits)." ;
365+ << " machine word size (" << word_type->getIntegerBitWidth () << " bits)." ;
366366
367367 if (val_size < word_size) {
368368 val = new llvm::ZExtInst (val, word_type, llvm::Twine::createNull (), block);
@@ -595,15 +595,19 @@ llvm::Value *InstructionLifter::LiftRegisterOperand(Instruction &inst,
595595 if (val_size < arg_size) {
596596 if (arg_type->isIntegerTy ()) {
597597 CHECK (val_type->isIntegerTy ())
598- << " Expected " << arch_reg.name << " to be an integral type "
598+ << " Expected " << arch_reg.name << " to be an integral type ("
599+ << " val_type: " << LLVMThingToString (val_type) << " , "
600+ << " arg_type: " << LLVMThingToString (arg_type) << " ) "
599601 << " for instruction at " << std::hex << inst.pc ;
600602
601603 val =
602604 new llvm::ZExtInst (val, arg_type, llvm::Twine::createNull (), block);
603605
604606 } else if (arg_type->isFloatingPointTy ()) {
605607 CHECK (val_type->isFloatingPointTy ())
606- << " Expected " << arch_reg.name << " to be a floating point type "
608+ << " Expected " << arch_reg.name << " to be a floating point type ("
609+ << " val_type: " << LLVMThingToString (val_type) << " , "
610+ << " arg_type: " << LLVMThingToString (arg_type) << " ) "
607611 << " for instruction at " << std::hex << inst.pc ;
608612
609613 val = new llvm::FPExtInst (val, arg_type, llvm::Twine::createNull (),
@@ -613,15 +617,19 @@ llvm::Value *InstructionLifter::LiftRegisterOperand(Instruction &inst,
613617 } else if (val_size > arg_size) {
614618 if (arg_type->isIntegerTy ()) {
615619 CHECK (val_type->isIntegerTy ())
616- << " Expected " << arch_reg.name << " to be an integral type "
620+ << " Expected " << arch_reg.name << " to be an integral type ("
621+ << " val_type: " << LLVMThingToString (val_type) << " , "
622+ << " arg_type: " << LLVMThingToString (arg_type) << " ) "
617623 << " for instruction at " << std::hex << inst.pc ;
618624
619625 val = new llvm::TruncInst (val, arg_type, llvm::Twine::createNull (),
620626 block);
621627
622628 } else if (arg_type->isFloatingPointTy ()) {
623629 CHECK (val_type->isFloatingPointTy ())
624- << " Expected " << arch_reg.name << " to be a floating point type "
630+ << " Expected " << arch_reg.name << " to be a floating point type ("
631+ << " val_type: " << LLVMThingToString (val_type) << " , "
632+ << " arg_type: " << LLVMThingToString (arg_type) << " ) "
625633 << " for instruction at " << std::hex << inst.pc ;
626634
627635 val = new llvm::FPTruncInst (val, arg_type, llvm::Twine::createNull (),
@@ -876,8 +884,8 @@ InstructionLifter::LiftOperand(Instruction &inst, llvm::BasicBlock *block,
876884
877885 case Operand::kTypeShiftRegister :
878886 CHECK (Operand::kActionRead == arch_op.action )
879- << " Can't write to a shift register operand "
880- << " for instruction at " << std::hex << inst.pc ;
887+ << " Can't write to a shift register operand " << " for instruction at "
888+ << std::hex << inst.pc ;
881889
882890 return LiftShiftRegisterOperand (inst, block, state_ptr, arg, arch_op);
883891
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