rvjit: Introduce loongarch64 backend

LoongArch is a RISC ISA developed by Loongson, Co., Ltd., and has
defined three variants, LA32R (R stands for "reduced"), LA32S, and LA64.
This port only targets LA64 variant, since 32-bit LoongArch hardware is
barely available on market, and only serves for embedded/education
purpose.

So far native linker is intentionally left unimplemented, and small
immediate loading and conditional branch generation could be further
optimized.

This port has succeeded to boot a general RISC-V distribution, and
passes the riscv-tests. I also verified the correctness with my
downstream RVVM co-simulation patches[1]. Benchmarking with
fp-disabled coremark, it achieves 7% of native performance, or 4.7x
speed up over the interpreter (1176 v.s. 16666 v.s. 250 iterations/sec).

Link: https://github.com/ziyao233/RVVM/tree/cosim # [1]
Signed-off-by: Yao Zi <me@ziyao.cc>

Author: ziyao233

project.mk

@@ -93,7 +93,7 @@ USE_JNI         ?= 0 # Enable JNI support in librvvm
 
 # Acceleration
 # Enable JIT by default on x86_64, arm64, riscv64
-USE_JIT ?= $(if $(filter x86_64 arm64 riscv64,$(ARCH)),1,0)
+USE_JIT ?= $(if $(filter x86_64 arm64 riscv64 loongarch64,$(ARCH)),1,0)
 USE_KVM ?= 0
 
 # Misc toggles for debugging host platform/compiler issues
@@ -146,7 +146,7 @@ override SRC_USE_LIBRETRO  := $(SRCDIR)/bindings/libretro/libretro.c
 override SRC_USE_JNI       := $(SRCDIR)/bindings/jni/rvvm_jni.c
 
 # Useflag dependencies
-override RVJIT_SUPPORTS_ARCH := $(if $(filter i386 x86_64 arm% riscv%,$(ARCH)),1)
+override RVJIT_SUPPORTS_ARCH := $(if $(filter i386 x86_64 arm% riscv% loongarch64,$(ARCH)),1)
 override DEPS_USE_JIT        := RVJIT_SUPPORTS_ARCH
 
 override DEPS_USE_X11       := USE_GUI

src/rvjit/rvjit.c

@@ -86,6 +86,12 @@ static void rvjit_flush_icache(const void* addr, size_t size)
     FlushInstructionCache(GetCurrentProcess(), start, size);
 #elif defined(RVJIT_ARM64) && defined(GNU_EXTS)
     rvjit_arm64_fluch_icache(start, size);
+#elif defined(RVJIT_LA64) && defined(GNU_EXTS)
+    // LoongArch maintains I/D cache coherency in hardware, but a barrier must
+    // be inserted to prevent pipeline hazard.
+    UNUSED(start);
+    UNUSED(size);
+    __asm__ __volatile__("ibar 0" : : : "memory");
 #elif defined(RVJIT_APPLE_SILICON)
     sys_icache_invalidate(start, size);
 #elif defined(RVJIT_RISCV) && defined(__linux__) && defined(__NR_riscv_flush_icache)

src/rvjit/rvjit.h

@@ -79,6 +79,12 @@ file, You can obtain one at https://mozilla.org/MPL/2.0/.
 #define RVJIT_ARM      1
 #define RVJIT_ABI_SYSV 1
 
+#elif (defined(__loongarch__) && __loongarch_lp64) || defined(_M_LOONGARCH64)
+
+#define RVJIT_LA64         1
+#define RVJIT_ABI_SYSV     1
+#define RVJIT_NATIVE_64BIT 1
+
 #else
 
 #error No JIT support for the target platform!!!

src/rvjit/rvjit_emit.c

@@ -19,6 +19,8 @@ file, You can obtain one at https://mozilla.org/MPL/2.0/.
 #include "rvjit_arm64.h"
 #elif RVJIT_ARM
 #include "rvjit_arm.h"
+#elif RVJIT_LA64
+#include "rvjit_la64.h"
 #endif
 
 #define REG_SRC            0x1
@@ -151,7 +153,7 @@ static regid_t rvjit_map_reg(rvjit_block_t* block, regid_t greg, regflags_t flag
         rvvm_fatal("Mapped RVJIT register is out of range!");
         return REG_ILL;
     }
-#if defined(RVJIT_RISCV)
+#if defined(RVJIT_RISCV) || defined(RVJIT_LA64)
     if (greg == RVJIT_REGISTER_ZERO) {
         return 0;
     }
@@ -166,7 +168,7 @@ static regid_t rvjit_map_reg(rvjit_block_t* block, regid_t greg, regflags_t flag
         block->regs[greg].flags = 0;
     }
     block->regs[greg].last_used = block->size;
-#if !defined(RVJIT_RISCV) && !defined(RVJIT_ARM64)
+#if !defined(RVJIT_RISCV) && !defined(RVJIT_ARM64) && !defined(RVJIT_LA64)
     if (greg == RVJIT_REGISTER_ZERO) {
         if (!(block->regs[greg].flags & REG_LOADED) || (block->regs[greg].flags & REG_DIRTY)) {
             rvjit_native_zero_reg(block, block->regs[greg].hreg);