rvjit: Introduce loongarch64 backend

[ziyao233]

LoongArch is a RISC ISA developed by Loongson, Co., Ltd., and has defined three variants, LA32R (R stands for "reduced"), LA32S, and LA64. This port only targets LA64 variant, since 32-bit LoongArch hardware is barely available on market, and only serves for embedded/education purpose.

So far native linker is intentionally left unimplemented, and small immediate loading and conditional branch generation could be further optimized.

This port has succeeded to boot a general RISC-V distribution, and passes the riscv-tests. I also verified the correctness with my downstream RVVM co-simulation patches[1]. Benchmarking with fp-disabled coremark, it achieves 7% of native performance, or 4.7x speed up over the interpreter (1176 v.s. 16666 v.s. 250 iterations/sec).

Link: https://github.com/ziyao233/RVVM/tree/cosim # [1]

[ziyao233]

Distribution booted on RVVM

[ziyao233]

Coremark results with JIT on Loongson 3A5000

# cat run2.log
2K validation run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 17744
Total time (secs): 17
Iterations/Sec   : 1176
Iterations       : 20000
Compiler version : Clang 21.1.8
Compiler flags   : -O2 -DPERFORMANCE_RUN=1  -lrt
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0x18f2
[0]crclist       : 0xe3c1
[0]crcmatrix     : 0x0747
[0]crcstate      : 0x8d84
[0]crcfinal      : 0xd304
Correct operation validated. See README.md for run and reporting rules.

With -nojit

$ cat run2.log
2K validation run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 12185
Total time (secs): 12
Iterations/Sec   : 16666
Iterations       : 200000
Compiler version : GCC15.3.0 20260612 (AOSC OS)
Compiler flags   : -O2 -DPERFORMANCE_RUN=1  -lrt
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0x18f2
[0]crclist       : 0xe3c1
[0]crcmatrix     : 0x0747
[0]crcstate      : 0x8d84
[0]crcfinal      : 0x5b5d
Correct operation validated. See README.md for run and reporting rules.

on the host,

$ cat ~/Source/coremark/run2.log
2K validation run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 12185
Total time (secs): 12
Iterations/Sec   : 16666
Iterations       : 200000
Compiler version : GCC15.3.0 20260612 (AOSC OS)
Compiler flags   : -O2 -DPERFORMANCE_RUN=1  -lrt
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0x18f2
[0]crclist       : 0xe3c1
[0]crcmatrix     : 0x0747
[0]crcstate      : 0x8d84
[0]crcfinal      : 0x5b5d
Correct operation validated. See README.md for run and reporting rules.

[LekKit]

Coremark results with JIT on Loongson 3A5000

I assume the results are accidentally swapped with -nojit results? A very welcome result, otherwise.

So far native linker is intentionally left unimplemented

How complicated would be to add support for this? I have some refactoring work ongoing in ARM64 / RISCV backends, which should expose a set of rvjit_host_jump() / rvjit_host_call() / rvjit_host_jump_reg() / rvjit_host_call_reg() / rvjit_host_ret() / rvjit_host_patchable_ret() / rvjit_host_patch_ret() / rvjit_host_patch_jump(), however the design is not yet final

I will review in more detail soon

[ziyao233]

Coremark results with JIT on Loongson 3A5000

I assume the results are accidentally swapped with -nojit results? A very welcome result, otherwise.

Oops, with -nojit it should be 250 iterations/sec at maximum, as mentioned in the commit message, and I accidentally paste the log on native here. With -nojit the log should look like,

# cat run2.log 
2K validation run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 16846
Total time (secs): 16
Iterations/Sec   : 187
Iterations       : 3000
Compiler version : Clang 21.1.8
Compiler flags   : -O2 -DPERFORMANCE_RUN=1  -lrt
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0x18f2
[0]crclist       : 0xe3c1
[0]crcmatrix     : 0x0747
[0]crcstate      : 0x8d84
[0]crcfinal      : 0x2717
Correct operation validated. See README.md for run and reporting rules.

(I failed to reproduce the 250 iterations/sec result again lol)

So far native linker is intentionally left unimplemented

How complicated would be to add support for this? I have some refactoring work ongoing in ARM64 / RISCV backends, which should expose a set of rvjit_host_jump() / rvjit_host_call() / rvjit_host_jump_reg() / rvjit_host_call_reg() / rvjit_host_ret() / rvjit_host_patchable_ret() / rvjit_host_patch_ret() / rvjit_host_patch_jump(), however the design is not yet final

I had a brief look and don't think it would be too complicated, but I'd like to put off some non-essential features so the changes are in a manageable size. And for patching branches/returns I'd probably add another helper function, so I think it would take another 30-70 lines.

I will review in more detail soon

Thanks for your time!