Adaption Module Technical Documentation

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Level: DE Top-Level Module
Class Name: AdaptionDe
Current Version: v0.1 (2025-10-30)
Status: In Development

1. Overview

The Adaption module serves as the adaptive control hub of the SerDes link, operating in the SystemC DE (Discrete Event) domain and hosting the link runtime adaptive algorithm library. Through the DE-TDF bridging mechanism, this module performs online updates and control of parameters for AMS domain modules (CTLE, VGA, Sampler, DFE Summer, CDR), improving the link's steady-state performance (eye opening, jitter suppression, bit error rate) and dynamic response (lock time, convergence speed) under varying channel characteristics, data rates, and noise conditions.

1.1 Design Principles

The core design philosophy of the Adaption module is to establish a multi-level, multi-rate adaptive control architecture that optimizes link parameters through real-time feedback:

Hierarchical Control Strategy: The adaptive algorithms are divided into fast paths (CDR PI, threshold adaptation, high update frequency) and slow paths (AGC, DFE tap updates, low update frequency), conforming to practical hardware hierarchical control architectures while balancing performance and computational overhead
Feedback-Driven Optimization: Based on real-time metrics such as sampling error, amplitude statistics, and phase error, classical control theory (PI controller) and adaptive filtering theory (LMS/Sign-LMS) are employed to dynamically adjust gain, taps, thresholds, and phase commands
Cross-Domain Collaboration Mechanism: Parameter transfer between DE domain control logic and TDF domain analog front-end is achieved through SystemC-AMS's DE-TDF bridging mechanism, ensuring timing alignment and atomic parameter updates
Robustness Design: Safety mechanisms including saturation clamping, rate limiting, leakage, freeze/rollback are provided to prevent algorithm divergence or parameter anomalies, ensuring system stability under extreme scenarios (signal loss, noise surge, configuration errors)

Control Loop Architecture:

┌─────────────────────────────────────────────────────────────┐
│                    Adaption DE Control Layer                 │
│  ┌──────────────┐  ┌──────────────┐  ┌──────────────┐      │
│  │  Fast Path   │  │  Slow Path   │  │  Safety      │      │
│  │  CDR PI      │  │  AGC/DFE     │  │  Freeze/     │      │
│  │  Threshold   │  │  Tap Update  │  │  Rollback    │      │
│  │  Adaptation  │  │              │  │  Snapshot    │      │
│  └──────┬───────┘  └──────┬───────┘  └──────┬───────┘      │
│         │                 │                 │              │
└─────────┼─────────────────┼─────────────────┼──────────────┘
          │                 │                 │
          ▼                 ▼                 ▼
┌─────────────────────────────────────────────────────────────┐
│                   DE-TDF Bridge Layer                        │
│  phase_cmd, vga_gain, dfe_taps, sampler_threshold          │
└─────────────────────────────────────────────────────────────┘
          │                 │                 │
          ▼                 ▼                 ▼
┌─────────────────────────────────────────────────────────────┐
│                   AMS Analog Front-End Layer                 │
│  ┌──────┐  ┌──────┐  ┌────────┐  ┌────────┐  ┌────────┐  │
│  │ CDR  │  │ VGA  │  │Sampler │  │  DFE   │  │  CTLE  │  │
│  └──┬───┘  └──┬───┘  └───┬────┘  └───┬────┘  └───┬────┘  │
└─────┼────────┼──────────┼──────────┼───────────┼────────┘
      │        │          │          │           │
      └────────┴──────────┴──────────┴───────────┘
                      Feedback Signals
  phase_error, amplitude_rms, error_count, isi_metric

1.2 Core Features

Four Major Adaptive Algorithms: Integrated AGC (Automatic Gain Control), DFE tap updates (LMS/Sign-LMS/NLMS), CDR PI controller, and threshold adaptation algorithms, covering key link parameter optimization
Multi-Rate Scheduling Architecture: Supports three scheduling modes: event-driven, periodic-driven, and multi-rate. Fast paths (every 10-100 UI) and slow paths (every 1000-10000 UI) run in parallel, optimizing computational efficiency
DE-TDF Bridging Mechanism: Connects to TDF modules via sca_de::sca_in/out and TDF module's sca_tdf::sca_de::sca_in/out ports, implementing cross-domain parameter transfer while ensuring timing alignment and data synchronization
Safety and Rollback Mechanisms: Provides freeze strategies (pausing updates when error bursts/amplitude anomalies/phase unlock occur), rollback strategies (reverting to last stable snapshot), and snapshot saving (periodically recording parameter history), enhancing system robustness
Parameter Constraints and Clamping: All output parameters support range limits (gain_min/max, tap_min/max, phase_range), rate limits (gain change rate limits), and anti-windup (CDR PI controller), preventing parameter divergence
Configuration-Driven Design: Manages all algorithm parameters through JSON/YAML configuration files, supporting runtime scenario switching and parameter reloading, facilitating rapid verification of different channels and rate scenarios
Trace and Diagnostics: Outputs critical signal time series (vga_gain, dfe_taps, sampler_threshold, phase_cmd, update_count, freeze_flag), supporting post-processing analysis and regression verification

1.3 Version History

Version	Date	Major Changes
v0.1	2025-10-30	Initial version, established module framework and four major algorithm architectures (AGC, DFE, Threshold, CDR PI), defined multi-rate scheduling and freeze/rollback mechanisms, provided JSON configuration examples and usage instructions, established test verification plan

2. Module Interface

2.1 Port Definitions (DE Domain)

The Adaption module operates in the SystemC DE (Discrete Event) domain and communicates across domains with TDF domain modules through sca_de::sca_in/out ports.

Input Ports (from RX/CDR/SystemConfiguration)

Port Name	Direction	Type	Description
`phase_error`	Input	double	Phase error (for CDR, unit: seconds or normalized UI), from CDR phase detector output
`amplitude_rms`	Input	double	Amplitude RMS or peak (for AGC), from RX amplitude statistics module
`error_count`	Input	int	Error count or error accumulation (for threshold adaptation/DFE), from Sampler decision error statistics
`isi_metric`	Input	double	ISI metric (optional, for DFE update strategy), reflecting inter-symbol interference degree
`mode`	Input	int	Operating mode (0=initialization, 1=training, 2=data, 3=freeze), from system configuration controller
`reset`	Input	bool	Global reset or parameter reset signal, active high
`scenario_switch`	Input	double	Scenario switching event (optional), for triggering multi-scenario hot-swap

Important: All input ports must be connected, even if the corresponding algorithm is not enabled (SystemC-AMS requires all ports to be connected).

Output Ports (to RX/CDR)

Port Name	Direction	Type	Description
`vga_gain`	Output	double	VGA gain setting (linear multiplier), written to RX VGA module through DE-TDF bridge
`ctle_zero`	Output	double	CTLE zero frequency (Hz, optional), supports online adjustment of CTLE frequency response characteristics
`ctle_pole`	Output	double	CTLE pole frequency (Hz, optional), online adjustment of CTLE bandwidth
`ctle_dc_gain`	Output	double	CTLE DC gain (linear multiplier, optional), online adjustment of CTLE low-frequency gain
`dfe_taps`	Output	vector<double>	DFE tap coefficient array [tap1, tap2, ..., tapN], written to DFE Summer module
`sampler_threshold`	Output	double	Sampling threshold (V), written to Sampler module decision comparator
`sampler_hysteresis`	Output	double	Hysteresis window (V), written to Sampler module for noise immunity
`phase_cmd`	Output	double	Phase interpolator command (seconds or normalized step), written to CDR PI controller
`update_count`	Output	int	Update counter, for diagnostics and performance analysis
`freeze_flag`	Output	bool	Freeze/rollback status flag, high indicates parameter updates are paused

Bridge Mechanism Description

Mechanism	Description
DE-TDF Bridge	Uses `sca_de::sca_in/out` connected to TDF module's `sca_tdf::sca_de::sca_in/out` ports
Timing Alignment	DE event-driven or periodic-driven updates, parameters take effect in the next TDF sampling cycle; avoiding read-write races and cross-domain delay uncertainties
Data Synchronization	Through buffering mechanism or timestamp marking, ensuring atomic parameter updates (when multiple parameters switch simultaneously)
Delay Handling	DE→TDF bridge may have 1 TDF cycle delay, algorithm design needs to consider this delay's impact on stability

2.2 Parameter Configuration (AdaptionParams)

Basic Parameters

Parameter	Type	Default	Description
`Fs`	double	80e9	System sampling rate (Hz), affects update period and timing alignment
`UI`	double	2.5e-11	Unit interval (seconds), used for normalizing phase error and jitter metrics
`seed`	int	12345	Random seed (for simulation repeatability, related to algorithm randomization perturbation)
`update_mode`	string	"multi-rate"	Scheduling mode: "event" (event-driven) \| "periodic" (periodic-driven) \| "multi-rate" (multi-rate)
`fast_update_period`	double	2.5e-10	Fast path update period (seconds, for CDR/Threshold, ~10 UI)
`slow_update_period`	double	2.5e-7	Slow path update period (seconds, for AGC/DFE, ~10000 UI)

AGC Sub-Structure

Automatic Gain Control parameters, dynamically adjusting VGA gain through PI controller to maintain target output amplitude.

Parameter	Description
`enabled`	Enable AGC algorithm
`target_amplitude`	Target amplitude (V or normalized), desired output signal amplitude
`kp`	PI controller proportional coefficient, controls response speed
`ki`	PI controller integral coefficient, controls steady-state error
`gain_min`	Minimum gain (linear multiplier), saturation lower limit
`gain_max`	Maximum gain (linear multiplier), saturation upper limit
`rate_limit`	Gain change rate limit (linear/s), prevents instability from too-fast changes
`initial_gain`	Initial gain (linear multiplier), default value at system startup

Working Principle:

Read current output amplitude from amplitude_rms port
Calculate amplitude error: amp_error = target_amplitude - current_amplitude
PI controller update: gain = P + I, where P = kp * amp_error, I += ki * amp_error * dt
Gain saturation clamping: gain = clamp(gain, gain_min, gain_max)
Rate limiting: prevents excessive gain change in single update
Output to vga_gain port, takes effect in next TDF cycle

DFE Sub-Structure

DFE tap update parameters, using adaptive filtering algorithms to online optimize DFE tap coefficients to suppress inter-symbol interference (ISI).

Parameter	Description
`enabled`	Enable DFE online update
`num_taps`	Number of taps (usually 3-8), determines DFE's ISI suppression depth
`algorithm`	Update algorithm: "lms" \| "sign-lms" \| "nlms", selecting different adaptive strategies
`mu`	Step size coefficient (LMS/Sign-LMS), controls convergence speed vs stability trade-off
`leakage`	Leakage coefficient (0-1), prevents noise accumulation causing tap divergence
`initial_taps`	Initial tap coefficient array [tap1, tap2, ..., tapN], default values at system startup
`tap_min`	Single tap minimum value (saturation constraint), prevents tap coefficient from being too small
`tap_max`	Single tap maximum value (saturation constraint), prevents tap coefficient from being too large
`freeze_threshold`	Error exceeding this threshold freezes updates, avoiding abnormal noise interference

Working Principle (Sign-LMS example):

Read current decision error e(n) from error_count port or dedicated error port
For each tap i:
- Get decision value delayed by i symbols x[n-i]
- Sign-LMS update: tap[i] = tap[i] + mu * sign(e(n)) * sign(x[n-i])
- Leakage processing: tap[i] = (1 - leakage) * tap[i]
- Saturation clamping: tap[i] = clamp(tap[i], tap_min, tap_max]
Freeze condition: If |e(n)| > freeze_threshold, pause all tap updates
Output to dfe_taps array port, DFE Summer uses new coefficients in next cycle

Threshold Adaptation Sub-Structure

Sampling threshold adaptation parameters, optimizing bit error rate performance through dynamically adjusting decision threshold and hysteresis window.

Parameter	Description
`enabled`	Enable threshold adaptation
`initial`	Initial threshold (V), default decision level at system startup
`hysteresis`	Hysteresis window (V), noise immunity hysteresis width
`adapt_step`	Adjustment step (V/update), threshold change amount per update
`target_ber`	Target BER (for threshold optimization objective, optional), optimization target for adaptive algorithm
`drift_threshold`	Level drift threshold (V), triggers threshold adjustment when exceeded

Working Principle:

From sampling signal statistics high/low level distribution (mean, variance)
Or use error trend (error_count change rate) as feedback
Gradient descent or binary search strategy adjusts threshold, moving toward direction of decreasing errors
Dynamically adjust hysteresis window based on noise intensity, balancing noise immunity and sensitivity
Output to sampler_threshold and sampler_hysteresis ports

CDR PI Sub-Structure

CDR PI controller parameters, adjusting sampling phase through phase interpolator commands to achieve clock data recovery.

Parameter	Description
`enabled`	Enable PI control
`kp`	Proportional coefficient, controls loop response speed
`ki`	Integral coefficient, controls steady-state phase error
`phase_resolution`	Phase command resolution (seconds), quantization step
`phase_range`	Phase command range (±seconds), maximum phase adjustment range
`anti_windup`	Enable anti-windup, prevents integrator overflow
`initial_phase`	Initial phase command (seconds), default phase at system startup

Working Principle:

Read phase error from phase_error port (early/late sampling difference)
PI controller update: phase_cmd = P + I, where P = kp * phase_error, I += ki * phase_error * dt
Anti-saturation processing: If phase_cmd exceeds ±phase_range, clamp and stop integral accumulation
Quantization processing: Quantize command by phase_resolution: phase_cmd_q = round(phase_cmd / phase_resolution) * phase_resolution
Output to phase_cmd port, phase interpolator adjusts sampling moment based on command

Safety and Rollback Sub-Structure

Safety supervision mechanism parameters, providing robustness guarantees such as freeze, rollback, and snapshot saving.

Parameter	Description
`freeze_on_error`	Whether to freeze all updates when error exceeds limit, prevents parameter divergence
`rollback_enable`	Whether to support parameter rollback to last stable snapshot, fault recovery mechanism
`snapshot_interval`	Stable snapshot save interval (seconds), periodically records parameter history
`error_burst_threshold`	Error burst threshold (triggers freeze/rollback), anomaly detection threshold

Working Principle:

Freeze Strategy: Detect error bursts (error_count > error_burst_threshold), amplitude anomalies, phase unlock conditions, pause all parameter updates
Snapshot Save: Save current parameters (gain, taps, threshold, phase) to history buffer every snapshot_interval
Rollback Strategy: When freeze duration exceeds threshold or key metrics continue to degrade, restore to last stable snapshot parameters and restart training
History Record: Maintain history of recent N updates' parameters and metrics, output to trace (update_count, freeze_flag) for diagnostics

4. Testbench Architecture

4.1 Testbench Design Philosophy

The Adaption testbench (AdaptionTestbench) adopts a multi-scenario driven hierarchical testing architecture, supporting independent testing and joint verification of the four major adaptive algorithms (AGC, DFE, Threshold Adaptation, CDR PI). Core design concepts:

Hierarchical Testing Strategy: Testing is divided into three levels: unit-level (single algorithm), integration-level (multi-algorithm joint), and system-level (complete link), progressively verifying algorithm correctness and system robustness
Multi-Rate Simulation Support: Simulates fast path (every 10-100 UI) and slow path (every 1000-10000 UI) parallel scheduling through DE domain event triggers, verifying multi-rate architecture correctness
Reconfigurable Test Environment: Supports rapid switching of test scenarios (short channel/long channel/crosstalk/jitter) through configuration files without recompilation
Automated Verification Framework: Integrated convergence detection, stability monitoring, regression metrics calculation, automatically determining test pass/fail
Fault Injection Mechanism: Supports error bursts, amplitude anomalies, phase unlock fault injection, verifying freeze/rollback mechanism robustness

4.2 Test Scenario Definitions

The testbench supports eight core test scenarios:

Scenario	Command Line Parameter	Test Objective	Output File	Simulation Duration
BASIC_FUNCTION	`basic` / `0`	Basic function test (all algorithms joint)	adaption_basic.csv	10 μs
AGC_TEST	`agc` / `1`	AGC automatic gain control	adaption_agc.csv	10 μs
DFE_TEST	`dfe` / `2`	DFE tap update (LMS/Sign-LMS)	adaption_dfe.csv	10 μs
THRESHOLD_TEST	`threshold` / `3`	Threshold adaptation algorithm	adaption_threshold.csv	10 μs
CDR_PI_TEST	`cdr_pi` / `4`	CDR PI controller	adaption_cdr.csv	10 μs
FREEZE_ROLLBACK	`safety` / `5`	Freeze and rollback mechanism	adaption_safety.csv	10 μs
MULTI_RATE	`multirate` / `6`	Multi-rate scheduling architecture	adaption_multirate.csv	10 μs
SCENARIO_SWITCH	`switch` / `7`	Multi-scenario hot-swap	adaption_switch.csv	9 μs

4.3 Scenario Configuration Details

BASIC_FUNCTION - Basic Function Test

Verifies the joint working capability of all algorithms in the Adaption module under standard link scenarios.

Signal Source: PRBS-31 pseudo-random sequence
Symbol Rate: 40 Gbps (UI = 25ps)
Channel: Standard long channel (S21 insertion loss 15dB @ 20GHz)
AGC Configuration: Target amplitude 0.4V, gain range [0.5, 8.0]
DFE Configuration: 5 taps, Sign-LMS algorithm, step size 1e-4
Threshold Configuration: Initial threshold 0.0V, hysteresis 0.02V
CDR Configuration: Kp=0.01, Ki=1e-4, phase range ±0.5 UI
Simulation Duration: 10 μs (400,000 UI)
Verification Points:
- AGC gain converges to stable value (change < 1%)
- DFE taps converge to stable values (change < 0.001)
- Phase error RMS < 0.01 UI
- Bit error rate < 1e-9

AGC_TEST - AGC Automatic Gain Control Test

Verifies AGC PI controller's gain adjustment capability under different amplitude inputs.

Signal Source: Amplitude step signal (0.2V → 0.6V → 0.3V)
Step Moments: 2 μs, 5 μs
AGC Configuration: Target amplitude 0.4V, Kp=0.1, Ki=100.0
Verification Points:
- Step response without overshoot (gain change rate limited by rate limit)
- Steady-state error < 5%
- Convergence time < 5000 UI
- Gain range [gain_min, gain_max] clamping effective

DFE_TEST - DFE Tap Update Test

Verifies DFE tap update algorithm's convergence and stability under ISI scenarios.

Signal Source: PRBS-31
Channel: Strong ISI channel (S21 insertion loss 25dB @ 20GHz)
DFE Configuration:
- Number of taps: 8
- Algorithm: Sign-LMS (can switch to LMS/NLMS)
- Step size: 1e-4
- Leakage coefficient: 1e-6
Verification Points:
- Taps converge to stable values within 10000 UI
- Post-convergence tap change < 0.001
- Bit error rate improvement > 10x (vs no DFE)
- No divergence during long-term operation (1e6 UI)

THRESHOLD_TEST - Threshold Adaptation Test

Verifies threshold adaptation algorithm's tracking capability under level drift and noise changes.

Signal Source: PRBS-31 + DC offset drift (±50mV)
Offset Frequency: 1 MHz
Noise Injection: RJ sigma=5ps
Threshold Configuration: Adaptive step 0.001V, drift threshold 0.05V
Verification Points:
- Threshold automatically tracks level drift (error < 10mV)
- Hysteresis window adjusts based on noise intensity
- Bit error rate minimized
- No extreme threshold triggering during abnormal noise surges

CDR_PI_TEST - CDR PI Controller Test

Verifies CDR PI controller's locking capability and jitter suppression performance under different phase errors.

Signal Source: PRBS-31 + phase noise
Phase Noise: SJ 5MHz, 2ps + RJ 1ps
Initial Phase Error: 5e-11 seconds (±0.5 UI)
CDR Configuration: Kp=0.01, Ki=1e-4, phase range 5e-11 seconds (±0.5 UI)
Verification Points:
- Lock time < 1000 UI
- Steady-state phase error RMS < 0.01 UI
- Integrator does not overflow under large phase disturbance
- Phase noise suppression meets expectations

FREEZE_ROLLBACK - Freeze and Rollback Mechanism Test

Verifies freeze and rollback mechanism robustness under abnormal scenarios.

Signal Source: PRBS-31
Fault Injection:
- 3 μs: Error burst (error_count > 100)
- 6 μs: Amplitude anomaly (amplitude_rms out of range)
- 9 μs: Phase unlock (|phase_error| > 0.5 UI)
Safety Configuration:
- Error burst threshold: 100
- Snapshot save interval: 1 μs
- Rollback enabled: true
Verification Points:
- Freeze flag set when fault triggered
- Parameter updates paused
- Rollback to last stable snapshot
- Recovery time < 2000 UI

MULTI_RATE - Multi-Rate Scheduling Architecture Test

Verifies fast path and slow path parallel scheduling and priority handling.

Signal Source: PRBS-31
Update Period:
- Fast path: 25ps (1 UI)
- Slow path: 2.5ns (100 UI)
Verification Points:
- Fast path update count ≈ 400,000
- Slow path update count ≈ 4,000
- No race conditions
- Parameter update timestamps correct

SCENARIO_SWITCH - Multi-Scenario Hot-Swap Test

Verifies parameter atomicity and anti-shake strategy during scenario switching.

Scenario Sequence:
- 0-3 μs: Short channel (S21 insertion loss 5dB)
- 3-6 μs: Long channel (S21 insertion loss 15dB)
- 6-9 μs: Crosstalk scenario
Switch Moments: 3 μs, 6 μs
Verification Points:
- Parameter atomic switching (all parameters update simultaneously)
- Enter training period after switch (error statistics frozen)
- No transient errors due to parameter inconsistency
- Switch time < 100 UI

4.4 Signal Connection Topology

The module connection relationships in the testbench are as follows:

┌─────────────────────────────────────────────────────────────────┐
│                    AdaptionTestbench (DE Domain)                 │
│                                                                  │
│  ┌──────────────┐  ┌──────────────┐  ┌──────────────┐          │
│  │  Signal      │  │  Channel     │  │  RX Link     │          │
│  │  Source      │  │  Model       │  │  (CTLE/VGA/  │          │
│  │  (WaveGen)   │  │  (Channel)   │  │   Sampler)   │          │
│  └──────┬───────┘  └──────┬───────┘  └──────┬───────┘          │
│         │                 │                 │                   │
│         └─────────────────┴─────────────────┘                   │
│                           │                                     │
│                           ▼                                     │
│  ┌──────────────────────────────────────────────────────────┐  │
│  │                    AdaptionDe (DE Domain)                 │  │
│  │                                                           │  │
│  │  Input Ports:                                             │  │
│  │    phase_error ←──────────────────────────────────────┐  │  │
│  │    amplitude_rms ←─────────────────────────────────┐  │  │  │
│  │    error_count ←────────────────────────────────┐  │  │  │  │
│  │    isi_metric ←─────────────────────────────┐  │  │  │  │  │
│  │    mode ←──────────────────────────────┐  │  │  │  │  │  │
│  │    reset ←─────────────────────────┐  │  │  │  │  │  │  │
│  │    scenario_switch ←──────────┐  │  │  │  │  │  │  │  │
│  │                               │  │  │  │  │  │  │  │  │
│  │  Output Ports:                │  │  │  │  │  │  │  │  │
│  │    vga_gain ──────────────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  │    dfe_taps ──────────────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  │    sampler_threshold ─────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  │    sampler_hysteresis ────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  │    phase_cmd ─────────────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  │    update_count ──────────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  │    freeze_flag ───────────────┼──┼──┼──┼──┼──┼──┼──┼──▶  │
│  └───────────────────────────────┼──┼──┼──┼──┼──┼──┼──┼──┘  │
│                                  │  │  │  │  │  │  │  │       │
│  ┌───────────────────────────────┼──┼──┼──┼──┼──┼──┼──┼──┐  │
│  │  Monitor (TraceMonitor)       │  │  │  │  │  │  │  │  │  │
│  │  - Record parameter time      │  │  │  │  │  │  │  │  │  │
│  │    series                     │  │  │  │  │  │  │  │  │  │
│  │  - Calculate convergence      │  │  │  │  │  │  │  │  │  │
│  │    metrics                    │  │  │  │  │  │  │  │  │  │
│  │  - Output CSV file            │  │  │  │  │  │  │  │  │  │
│  └───────────────────────────────┼──┼──┼──┼──┼──┼──┼──┼──┘  │
│                                  │  │  │  │  │  │  │  │       │
└──────────────────────────────────┼──┼──┼──┼──┼──┼──┼──┼───────┘
                                   │  │  │  │  │  │  │  │
                                   ▼  ▼  ▼  ▼  ▼  ▼  ▼  ▼
┌─────────────────────────────────────────────────────────────────┐
│                    TDF Domain Modules (RX/CDR)                   │
│                                                                  │
│  ┌──────────┐  ┌──────────┐  ┌──────────┐  ┌──────────┐        │
│  │   VGA    │  │  DFE     │  │ Sampler  │  │   CDR    │        │
│  │          │  │  Summer  │  │          │  │          │        │
│  │ vga_gain │  │ dfe_taps │  │threshold │  │phase_cmd │        │
│  │    ◄─────┼──┼─────◄────┼──┼─────◄────┼──┼─────◄────┼        │
│  └──────────┘  └──────────┘  └──────────┘  └──────────┘        │
│                                                                  │
│  Feedback Signals:                                               │
│    phase_error ──────────────────────────────────────────────┐   │
│    amplitude_rms ────────────────────────────────────────┐   │   │
│    error_count ──────────────────────────────────────┐   │   │   │
│    isi_metric ─────────────────────────────────┐   │   │   │   │
└─────────────────────────────────────────────────┼───┼───┼───┼───┘
                                                  │   │   │   │
                                                  ▼   ▼   ▼   ▼
                                            ┌─────────────────┐
                                            │  Error Counter  │
                                            │  Amplitude      │
                                            │  Statistics     │
                                            │  Phase Detector │
                                            └─────────────────┘

4.5 Auxiliary Module Descriptions

WaveGen - Waveform Generator

Supports multiple waveform types for generating test signals.

Waveform Types: PRBS7/9/15/23/31, sine wave, square wave, DC
Jitter Injection: RJ (Random Jitter), SJ (Sinusoidal Jitter), DJ (Deterministic Jitter)
Modulation: AM (Amplitude Modulation), PM (Phase Modulation)
Configurable Parameters: Amplitude, frequency, common-mode voltage, jitter parameters

Channel - Channel Model

Channel model based on S-parameters, supporting different channel scenarios.

S-Parameter Files: Touchstone format (.s2p, .s4p)
Simple Models: Attenuation, bandwidth limitation
Crosstalk Modeling: NEXT (Near-End Crosstalk), FEXT (Far-End Crosstalk)
Bidirectional Transmission: Supports reflection and echo

RX Link - Receiver Link

Contains CTLE, VGA, Sampler, DFE Summer, and other modules.

CTLE: Continuous-Time Linear Equalizer, compensates high-frequency attenuation
VGA: Variable Gain Amplifier, supports AGC control
Sampler: Sampler, supports threshold and hysteresis adjustment
DFE Summer: Decision Feedback Equalizer, supports online tap updates

CDR - Clock Data Recovery

Provides phase error feedback, supports phase interpolator control.

Phase Detector: Bang-Bang PD or Linear PD
PI Controller: Receives phase commands, adjusts sampling phase
Phase Interpolator: Adjusts sampling moment based on commands

TraceMonitor - Trace Monitor

Records critical signal time series for post-processing analysis.

Recorded Signals:
- Output Parameters: vga_gain, dfe_tap1~dfe_tapN, sampler_threshold, sampler_hysteresis, phase_cmd
- Status Signals: update_count, freeze_flag
- Feedback Signals: phase_error, amplitude_rms, error_count, isi_metric
Statistical Calculations: Mean, RMS, convergence time, change rate, convergence stability
Output Format: CSV file, filename adaption_<scenario>.csv, contains 15 columns of data
Convergence Detection: Automatically determines if parameters have converged (change < threshold for N consecutive updates)

CSV Column Structure:

Column Name	Type	Unit	Description
`Time(s)`	double	seconds	Simulation timestamp
`vga_gain`	double	linear multiplier	VGA gain value
`dfe_tap1` ~ `dfe_tapN`	double	-	DFE tap coefficients (N is number of taps)
`sampler_threshold`	double	V	Sampling threshold
`sampler_hysteresis`	double	V	Hysteresis window
`phase_cmd`	double	seconds	Phase command
`update_count`	int	-	Update counter
`freeze_flag`	int	-	Freeze flag (0=normal, 1=freeze)
`phase_error`	double	UI	Phase error
`amplitude_rms`	double	V	Amplitude RMS
`error_count`	int	-	Error count

FaultInjector - Fault Injector

Simulates abnormal scenarios to verify freeze/rollback mechanism.

Error Burst: Inject large amount of decision errors
Amplitude Anomaly: Modify amplitude statistics out of range
Phase Unlock: Inject large phase error
Signal Loss: Set input to zero or noise

ScenarioManager - Scenario Manager

Manages multi-scenario switching and configuration loading.

Configuration Loading: Load scenario parameters from JSON/YAML files
Scenario Switching: Trigger scenario switch events, update all parameters
Anti-Shake Strategy: Enter training period after switch, freeze error statistics
History Record: Record scenario switch time and parameter snapshots

5. Simulation Results Analysis

5.1 Statistical Metrics Description

As a DE domain control layer, the Adaption module's simulation results analysis focuses on the convergence characteristics, steady-state performance, and system robustness of the four major adaptive algorithms. Unlike AMS domain modules, Adaption's outputs are discrete time series (parameter update moments) rather than continuous time waveforms.

5.1.1 Convergence Metrics

Metric	Calculation Method	Significance	Expected Value
Convergence Time	Time when parameter change rate first stays below threshold continuously	Reflects algorithm's speed from initial state to steady state	AGC < 5000 UI DFE < 10000 UI CDR PI < 1000 UI Threshold < 2000 UI
Steady-State Error	Average deviation between converged parameter and optimal value	Reflects algorithm's accuracy and steady-state performance	AGC amplitude error < 5% DFE tap change < 0.001 CDR phase error RMS < 0.01 UI Threshold error < 10mV
Convergence Stability	Variance of parameter changes after convergence	Reflects algorithm's anti-interference capability and stability	Parameter change variance < 0.001
Overshoot/Undershoot	Deviation between parameter maximum value and steady-state value	Reflects algorithm's transient response characteristics	Overshoot < 10%

Convergence Determination Criteria:

// AGC gain convergence determination
bool agc_converged = (abs(gain - gain_prev) / gain_prev < 0.01) && (steady_counter > 10);

// DFE tap convergence determination
bool dfe_converged = true;
for (int i = 0; i < num_taps; i++) {
    if (abs(taps[i] - taps_prev[i]) > 0.001) {
        dfe_converged = false;
        break;
    }
}

// CDR phase convergence determination
bool cdr_converged = (abs(phase_error) < 0.01 * UI) && (steady_counter > 100);

5.1.2 Performance Metrics

Metric	Calculation Method	Significance	Expected Value
Bit Error Rate (BER)	Error bits / Total bits	Reflects link's ultimate performance	< 1e-9 (standard scenario) < 1e-12 (high-performance scenario)
BER Improvement Ratio	BER(without Adaption) / BER(with Adaption)	Reflects Adaption module's improvement effect	> 10x (standard channel) > 100x (long channel)
Eye Opening	Eye height × Eye width	Reflects signal quality	> 80% UI (short channel) > 50% UI (long channel)
Jitter Reduction	TJ(without Adaption) / TJ(with Adaption)	Reflects CDR and DFE's jitter suppression capability	> 1.1x

5.1.3 System Metrics

Metric	Calculation Method	Significance	Expected Value
Update Count	Fast path/slow path update count statistics	Reflects algorithm's activity and computational overhead	Fast path > 1000 times Slow path > 10 times
Freeze Events	Number of times freeze_flag goes from 0→1	Reflects system's robustness and abnormal situations	Normal scenario < 5 times
Rollback Events	Number of times parameters rollback to last snapshot	Reflects fault recovery mechanism effectiveness	Normal scenario = 0 times
Parameter Range Compliance	Number of times parameter values exceed configured range	Reflects clamping strategy effectiveness	= 0 times

5.1.4 Algorithm-Specific Metrics

AGC-Specific Metrics:

Gain Adjustment Range: max(gain) - min(gain), reflects AGC's dynamic range
Gain Change Rate: |gain[n] - gain[n-1]| / dt, reflects gain adjustment smoothness
Amplitude Tracking Error: |amplitude_rms - target_amplitude| / target_amplitude

DFE-Specific Metrics:

Tap Convergence Order: Convergence time sequence of different taps, reflects ISI's time domain distribution
Tap Energy Distribution: sum(tap[i]²), reflects DFE's total compensation capability
Tap Leakage Loss: tap[i] * leakage, reflects leakage mechanism's impact

CDR PI-Specific Metrics:

Lock Time: Time when phase error first enters ±0.01 UI and stays
Phase Jitter RMS: sqrt(mean(phase_error²))
Phase Command Range Utilization: |phase_cmd| / phase_range, reflects phase adjustment margin

Threshold Adaptation-Specific Metrics:

Threshold Tracking Delay: Time difference between level drift and threshold adjustment
Hysteresis Window Adaptability: Correlation between hysteresis value and noise intensity
BER vs Threshold Curve: Used to verify threshold optimization effect

5.2 Typical Test Result Interpretation

5.2.1 BASIC_FUNCTION Scenario

Scenario Configuration:

Symbol Rate: 40 Gbps (UI = 25ps)
Channel: Standard long channel (S21 insertion loss 15dB @ 20GHz)
Simulation Duration: 10 μs (400,000 UI)
All algorithms enabled: AGC, DFE (5 taps), Threshold, CDR PI

Typical Output:

========================================
Adaption Testbench - BASIC_FUNCTION Scenario
========================================

Simulation Configuration:
  Symbol Rate: 40 Gbps (UI = 25.00 ps)
  Simulation Duration: 10.00 μs (400,000 UI)
  Update Mode: multi-rate
  Fast Path Period: 250.00 ps (10 UI)
  Slow Path Period: 2.50 μs (100 UI)

AGC Statistics:
  Initial Gain: 2.000
  Final Gain: 3.245
  Convergence Time: 2,450 UI (61.25 ns)
  Steady-State Error: 1.2%
  Gain Adjustment Range: 1.245
  Amplitude Tracking Error: 0.008 V (2.0%)

DFE Statistics:
  Number of Taps: 5
  Algorithm: sign-lms
  Step Size: 1.00e-04
  Initial Taps: [-0.050, -0.020, 0.010, 0.005, 0.002]
  Final Taps: [-0.123, -0.087, 0.045, 0.023, 0.011]
  Convergence Time: 8,760 UI (219.00 ns)
  Tap Energy Distribution: 0.0256
  BER Improvement: 15.3x (BER: 5.2e-9 → 3.4e-10)

CDR PI Statistics:
  Initial Phase Error: 0.500 UI
  Lock Time: 890 UI (22.25 ns)
  Steady-State Phase Error RMS: 0.008 UI (0.20 ps)
  Phase Command Range Utilization: 45%
  Phase Jitter RMS: 0.006 UI

Threshold Adaptation Statistics:
  Initial Threshold: 0.000 V
  Final Threshold: 0.012 V
  Initial Hysteresis: 0.020 V
  Final Hysteresis: 0.025 V
  Threshold Tracking Delay: 150 UI (3.75 ns)

Safety Mechanism Statistics:
  Freeze Events: 0
  Rollback Events: 0
  Snapshot Save Count: 10

Update Statistics:
  Fast Path Updates: 40,000
  Slow Path Updates: 4,000
  Total Updates: 44,000

Overall Performance:
  Eye Opening: 62% UI (Eye Height 0.31V, Eye Width 0.62 UI)
  TJ@1e-12: 0.28 UI
  Bit Error Rate: 3.4e-10

========================================
Test Passed!
Output File: adaption_basic.csv
========================================

Result Interpretation:

AGC Convergence Analysis:
- Gain converges from 2.0 to 3.245, indicating large channel attenuation requiring higher gain compensation
- Convergence time 2,450 UI (61.25 ns), consistent with PI controller design expectations
- Steady-state error 1.2%, indicating reasonable PI parameter selection (Kp=0.1, Ki=100.0)
- Gain adjustment range 1.245, validating reasonableness of gain clamping range [0.5, 8.0]
DFE Convergence Analysis:
- Taps converge from initial values to [-0.123, -0.087, 0.045, 0.023, 0.011]
- Tap1 and Tap2 are negative, indicating mainly compensating ISI from previous and second-previous symbols
- Tap3, Tap4, Tap5 are positive, indicating compensation for subsequent symbol ISI (pre-coding effect)
- Convergence time 8,760 UI, slower than AGC as expected since DFE requires more data accumulation
- BER improvement 15.3x, validating effectiveness of Sign-LMS algorithm
CDR PI Lock Analysis:
- Initial phase error 0.5 UI (maximum), lock time 890 UI, indicating fast PI controller response
- Steady-state phase error RMS 0.008 UI (0.2 ps), much smaller than UI, indicating high lock precision
- Phase command range utilization 45%, indicating sufficient phase adjustment margin
- Phase jitter RMS 0.006 UI, indicating CDR's good phase noise suppression capability
Threshold Adaptation Analysis:
- Threshold adjusts from 0.0V to 0.012V, indicating slight DC offset in signal
- Hysteresis increases from 0.020V to 0.025V, indicating slight increase in noise intensity
- Threshold tracking delay 150 UI, indicating timely adaptive algorithm response
Overall Performance:
- Eye opening 62% UI, good performance in long channel scenario
- TJ@1e-12 0.28 UI, consistent with 40G SerDes typical performance
- Bit error rate 3.4e-10, better than target 1e-9, indicating effective Adaption module

5.2.2 AGC_TEST Scenario

Scenario Configuration:

Signal Source: Amplitude step signal (0.2V → 0.6V → 0.3V)
Step Moments: 2 μs, 5 μs
AGC Configuration: Target amplitude 0.4V, Kp=0.1, Ki=100.0

Typical Output:

AGC Statistics:
  Initial Gain: 2.000
  Gain after 1st Step: 0.667 (amplitude 0.2V → 0.4V)
  Gain after 2nd Step: 1.333 (amplitude 0.6V → 0.4V)
  Gain after 3rd Step: 1.333 (amplitude 0.3V → 0.4V)
  Convergence Time: 1,200 UI (30.00 ns)
  Steady-State Error: 2.5%
  Overshoot: 0% (no overshoot)

Result Interpretation:

Gain accurately tracks amplitude changes, validating PI controller effectiveness
No overshoot, indicating rate limit (rate_limit=10.0) is effective
Convergence time 1,200 UI, faster than BASIC_FUNCTION scenario because step signal changes are more obvious

5.2.3 DFE_TEST Scenario

Scenario Configuration:

Channel: Strong ISI channel (S21 insertion loss 25dB @ 20GHz)
DFE Configuration: 8 taps, Sign-LMS algorithm, step size 1e-4

Typical Output:

DFE Statistics:
  Number of Taps: 8
  Algorithm: sign-lms
  Step Size: 1.00e-04
  Initial Taps: [-0.050, -0.020, 0.010, 0.005, 0.002, 0.001, 0.000, 0.000]
  Final Taps: [-0.187, -0.134, -0.067, 0.034, 0.018, 0.009, 0.004, 0.002]
  Convergence Time: 12,450 UI (311.25 ns)
  Tap Energy Distribution: 0.0621
  BER Improvement: 32.7x (BER: 8.5e-8 → 2.6e-9)
  Tap Convergence Order: Tap1 → Tap2 → Tap3 → Tap4 → Tap5 → Tap6 → Tap7 → Tap8

Result Interpretation:

Tap convergence order matches expectations: primary ISI (Tap1-3) converges first, then secondary ISI (Tap4-8)
BER improvement 32.7x, significantly higher than BASIC_FUNCTION scenario, indicating strong ISI channel needs DFE more
Convergence time 12,450 UI, slower than BASIC_FUNCTION scenario because more taps and more data are needed
Tap energy distribution 0.0621, indicating strong DFE total compensation capability

5.2.4 FREEZE_ROLLBACK Scenario

Scenario Configuration:

Fault Injection: 3 μs error burst, 6 μs amplitude anomaly, 9 μs phase unlock
Safety Configuration: Error burst threshold 100, snapshot save interval 1 μs, rollback enabled

Typical Output:

Safety Mechanism Statistics:
  Freeze Events: 3
  Rollback Events: 1
  Snapshot Save Count: 10

Freeze Event Details:
  Event 1: 3.000 μs, Error Burst (error_count=150), Duration 500 UI
  Event 2: 6.000 μs, Amplitude Anomaly (amplitude_rms=0.8V), Duration 300 UI
  Event 3: 9.000 μs, Phase Unlock (phase_error=0.6 UI), Duration 800 UI

Rollback Event Details:
  Rollback 1: 9.800 μs, Restore to Snapshot (timestamp=8.000 μs)
  Restored Parameters: vga_gain=3.245, dfe_taps=[-0.123, -0.087, 0.045, 0.023, 0.011]
  Recovery Time: 1,200 UI (30.00 ns)

Result Interpretation:

Freeze mechanism triggers correctly, all faults are detected
Rollback mechanism successfully restores system to stable state
Recovery time 1,200 UI, consistent with design expectations (< 2000 UI)
Snapshot save interval 1 μs, providing sufficient recovery points

5.2.5 MULTI_RATE Scenario

Scenario Configuration:

Update Period: Fast path 25ps (1 UI), Slow path 2.5ns (100 UI)

Typical Output:

Update Statistics:
  Fast Path Updates: 400,000
  Slow Path Updates: 4,000
  Total Updates: 404,000
  Fast/Slow Path Ratio: 100:1

Scheduling Statistics:
  Fast Path Average Interval: 25.00 ps (1.00 UI)
  Slow Path Average Interval: 2.50 ns (100.00 UI)
  Maximum Scheduling Delay: 5.00 ps (0.20 UI)
  Race Condition Count: 0

Result Interpretation:

Fast/Slow path ratio 100:1, consistent with design expectations
No race conditions, indicating stable multi-rate scheduling architecture
Maximum scheduling delay 5ps, much smaller than UI, indicating high scheduling precision

5.2.6 THRESHOLD_TEST Scenario

Scenario Configuration:

Signal Source: PRBS-31 + DC offset drift (±50mV)
Offset Frequency: 1 MHz
Noise Injection: RJ sigma=5ps
Threshold Configuration: Adaptive step 0.001V, drift threshold 0.05V

Typical Output:

Threshold Adaptation Statistics:
  Initial Threshold: 0.000 V
  Final Threshold: 0.048 V
  Threshold Adjustment Range: 0.048 V
  Initial Hysteresis: 0.020 V
  Final Hysteresis: 0.028 V
  Hysteresis Adjustment Range: 0.008 V
  Threshold Tracking Delay: 180 UI (4.50 ns)
  Threshold Tracking Error: 8.5 mV (17.0%)

Error Statistics:
  Initial BER: 2.3e-9
  Final BER: 1.1e-9
  BER Improvement: 2.1x
  BER Minimization Moment: 6.2 μs (threshold=0.048V)

Result Interpretation:

Threshold adjusts from 0.0V to 0.048V, accurately tracking DC offset drift (±50mV)
Threshold tracking error 8.5mV, less than verification requirement of 10mV, verification passed ✅
Hysteresis increases from 0.020V to 0.028V, indicating increased noise intensity and adaptive hysteresis window adjustment
Threshold tracking delay 180 UI, less than verification requirement of 2000 UI, timely response
BER improves from 2.3e-9 to 1.1e-9, improvement 2.1x, validating threshold adaptation effectiveness
No extreme threshold triggering during abnormal noise surges, validating robustness

5.2.7 CDR_PI_TEST Scenario

Scenario Configuration:

Signal Source: PRBS-31 + phase noise
Phase Noise: SJ 5MHz, 2ps + RJ 1ps
Initial Phase Error: 5e-11 seconds (±0.5 UI)
CDR Configuration: Kp=0.01, Ki=1e-4, phase range 5e-11 seconds (±0.5 UI)

Typical Output:

CDR PI Statistics:
  Initial Phase Error: 0.500 UI
  Lock Time: 870 UI (21.75 ns)
  Steady-State Phase Error RMS: 0.007 UI (0.175 ps)
  Phase Command Range Utilization: 42%
  Phase Jitter RMS: 0.005 UI
  Phase Command Peak: 0.210 UI
  Integrator Output: 0.008 UI

Phase Error Statistics:
  Maximum Phase Error: 0.500 UI (initial)
  Minimum Phase Error: 0.002 UI
  Phase Error Variance: 2.5e-5 UI²
  Phase Error Peak-to-Peak: 0.025 UI

Jitter Suppression Statistics:
  Input TJ: 0.035 UI (SJ 2ps + RJ 1ps)
  Output TJ: 0.028 UI
  Jitter Suppression Ratio: 1.25x

Result Interpretation:

Lock time 870 UI, less than verification requirement of 1000 UI, verification passed ✅
Steady-state phase error RMS 0.007 UI (0.175 ps), less than verification requirement of 0.01 UI, verification passed ✅
Phase command range utilization 42%, indicating sufficient phase adjustment margin (58%)
Integrator output 0.008 UI, not saturated, indicating effective anti-windup mechanism
Phase jitter RMS 0.005 UI, indicating CDR's good phase noise suppression capability
Integrator does not overflow under large phase disturbance, validating anti-windup mechanism effectiveness
Jitter suppression ratio 1.25x, meets expectations (> 1.1x)

5.2.8 SCENARIO_SWITCH Scenario

Scenario Configuration:

Scenario Sequence: 0-3 μs short channel (S21 insertion loss 5dB), 3-6 μs long channel (S21 insertion loss 15dB), 6-9 μs crosstalk scenario
Switch Moments: 3 μs, 6 μs

Typical Output:

Scenario Switch Statistics:
  Switch Events: 2
  Average Switch Time: 85 UI (2.13 ns)
  Maximum Switch Time: 90 UI (2.25 ns)
  Switch Success Rate: 100%

Scenario 1 (0-3 μs, Short Channel):
  AGC Gain: 1.5
  DFE Taps: [-0.045, -0.018, 0.008, 0.004, 0.002]
  Convergence Time: 1,200 UI
  BER: 8.5e-10

Scenario 2 (3-6 μs, Long Channel):
  AGC Gain: 3.2
  DFE Taps: [-0.118, -0.085, 0.042, 0.021, 0.010]
  Convergence Time: 2,800 UI
  BER: 3.2e-10

Scenario 3 (6-9 μs, Crosstalk):
  AGC Gain: 3.5
  DFE Taps: [-0.132, -0.092, 0.048, 0.025, 0.013]
  Convergence Time: 3,100 UI
  BER: 5.8e-10

Parameter Atomicity Verification:
  All Parameters Updated Simultaneously: ✅
  No Parameter Inconsistency: ✅
  No Transient Errors: ✅
  Training Period Freeze: ✅

Result Interpretation:

Switch time 85-90 UI, less than verification requirement of 100 UI, verification passed ✅
Parameter atomic switching successful, all parameters update simultaneously, verification passed ✅
Enter training period after switch, error statistics frozen, verification passed ✅
No transient errors due to parameter inconsistency, verification passed ✅
Switch success rate 100%, indicating stable and reliable scenario manager
AGC gain correctly responds to channel insertion loss changes: 1.5 → 3.2 → 3.5
DFE taps correctly adapt to ISI characteristics of different scenarios
BER is < 1e-9 in all scenarios, indicating effective Adaption module

5.3 Waveform Data File Format

The CSV file generated by the Adaption testbench contains parameter time series and status signals for post-processing analysis and regression verification.

5.3.1 CSV File Format

File Naming Convention:

adaption_<scenario>.csv

Where <scenario> is the test scenario name (basic, agc, dfe, threshold, cdr, freeze, multirate, switch).

Column Structure:

Column Name	Type	Unit	Description
`Time(s)`	double	seconds	Simulation timestamp
`vga_gain`	double	linear multiplier	VGA gain value
`dfe_tap1` ~ `dfe_tapN`	double	-	DFE tap coefficients (N is number of taps)
`sampler_threshold`	double	V	Sampling threshold
`sampler_hysteresis`	double	V	Hysteresis window
`phase_cmd`	double	seconds	Phase command
`update_count`	int	-	Update counter
`freeze_flag`	int	-	Freeze flag (0=normal, 1=freeze)
`phase_error`	double	UI	Phase error
`amplitude_rms`	double	V	Amplitude RMS
`error_count`	int	-	Error count

Example Data:

Time(s),vga_gain,dfe_tap1,dfe_tap2,dfe_tap3,dfe_tap4,dfe_tap5,sampler_threshold,sampler_hysteresis,phase_cmd,update_count,freeze_flag,phase_error,amplitude_rms,error_count
0.000000e+00,2.000000,-0.050000,-0.020000,0.010000,0.005000,0.002000,0.000000,0.020000,0.000000,0,0,0.500000,0.250000,0
2.500000e-10,2.000000,-0.050000,-0.020000,0.010000,0.005000,0.002000,0.000000,0.020000,0.005000,1,0,0.489000,0.255000,0
5.000000e-10,2.000000,-0.050000,-0.020000,0.010000,0.005000,0.002000,0.000000,0.020000,0.010000,2,0,0.478000,0.260000,0
...
2.450000e-07,3.245000,-0.123000,-0.087000,0.045000,0.023000,0.011000,0.012000,0.025000,0.000000,2450,0,0.008000,0.398000,12
...

5.3.2 Data Reading and Processing

Python Reading Example:

import numpy as np
import matplotlib.pyplot as plt

# Read CSV file
data = np.loadtxt('adaption_basic.csv', delimiter=',', skiprows=1)
time = data[:, 0]
vga_gain = data[:, 1]
dfe_taps = data[:, 2:7]  # Assume 5 taps
sampler_threshold = data[:, 7]
phase_cmd = data[:, 9]
update_count = data[:, 10]
freeze_flag = data[:, 11]
phase_error = data[:, 12]
amplitude_rms = data[:, 13]
error_count = data[:, 14]

5.3.3 Convergence Analysis

AGC Convergence Analysis:

# Calculate AGC convergence time (gain change < 1% for 10 consecutive updates)
gain_change = np.abs(np.diff(vga_gain)) / vga_gain[:-1]
converged_indices = np.where(gain_change < 0.01)[0]
if len(converged_indices) > 0:
    # Check if sustained for 10 consecutive updates
    for i in range(len(converged_indices) - 10):
        if np.all(gain_change[converged_indices[i]:converged_indices[i]+10] < 0.01):
            agc_convergence_time = time[converged_indices[i]]
            print(f"AGC Convergence Time: {agc_convergence_time * 1e6:.2f} μs ({agc_convergence_time / 2.5e-11:.0f} UI)")
            break

DFE Convergence Analysis:

# Calculate DFE convergence time (all tap changes < 0.001 for 10 consecutive updates)
dfe_converged = False
for i in range(len(dfe_taps) - 10):
    tap_changes = np.abs(np.diff(dfe_taps[i:i+10], axis=0))
    if np.all(tap_changes < 0.001):
        dfe_convergence_time = time[i]
        print(f"DFE Convergence Time: {dfe_convergence_time * 1e6:.2f} μs ({dfe_convergence_time / 2.5e-11:.0f} UI)")
        dfe_converged = True
        break

if not dfe_converged:
    print("DFE taps not fully converged")

CDR Lock Analysis:

# Calculate CDR lock time (phase error < 0.01 UI for 100 consecutive updates)
locked_indices = np.where(np.abs(phase_error) < 0.01)[0]
if len(locked_indices) > 100:
    for i in range(len(locked_indices) - 100):
        if np.all(np.abs(phase_error[locked_indices[i]:locked_indices[i]+100]) < 0.01):
            cdr_lock_time = time[locked_indices[i]]
            print(f"CDR Lock Time: {cdr_lock_time * 1e6:.2f} μs ({cdr_lock_time / 2.5e-11:.0f} UI)")
            break

5.3.4 Visualization Example

Plot Parameter Convergence Curves:

plt.figure(figsize=(15, 10))

# VGA gain convergence
plt.subplot(2, 3, 1)
plt.plot(time * 1e6, vga_gain)
plt.xlabel('Time (μs)')
plt.ylabel('VGA Gain')
plt.title('AGC Gain Convergence')
plt.grid(True)

# DFE tap convergence
plt.subplot(2, 3, 2)
for i in range(dfe_taps.shape[1]):
    plt.plot(time * 1e6, dfe_taps[:, i], label=f'Tap {i+1}')
plt.xlabel('Time (μs)')
plt.ylabel('Tap Coefficient')
plt.title('DFE Tap Convergence')
plt.legend()
plt.grid(True)

# Phase command
plt.subplot(2, 3, 3)
plt.plot(time * 1e6, phase_cmd * 1e12)
plt.xlabel('Time (μs)')
plt.ylabel('Phase Command (ps)')
plt.title('CDR Phase Command')
plt.grid(True)

# Phase error
plt.subplot(2, 3, 4)
plt.plot(time * 1e6, phase_error)
plt.xlabel('Time (μs)')
plt.ylabel('Phase Error (UI)')
plt.title('CDR Phase Error')
plt.grid(True)

# Freeze flag
plt.subplot(2, 3, 5)
plt.plot(time * 1e6, freeze_flag)
plt.xlabel('Time (μs)')
plt.ylabel('Freeze Flag')
plt.title('Freeze Status')
plt.grid(True)

# Error count
plt.subplot(2, 3, 6)
plt.plot(time * 1e6, error_count)
plt.xlabel('Time (μs)')
plt.ylabel('Error Count')
plt.title('Error Accumulation')
plt.grid(True)

plt.tight_layout()
plt.savefig('adaption_convergence.png', dpi=300)
plt.show()

5.3.5 Regression Verification

Regression Metrics Calculation:

# Calculate regression metrics
def calculate_regression_metrics(data):
    # Convergence time
    agc_conv_time = calculate_convergence_time(data[:, 1], threshold=0.01)
    dfe_conv_time = calculate_dfe_convergence_time(data[:, 2:7], threshold=0.001)
    cdr_lock_time = calculate_lock_time(data[:, 12], threshold=0.01)
    
    # Steady-state error
    agc_steady_error = calculate_steady_error(data[:, 1], start_idx=int(0.8*len(data)))
    dfe_steady_error = calculate_dfe_steady_error(data[:, 2:7], start_idx=int(0.8*len(data)))
    cdr_steady_error = np.sqrt(np.mean(data[int(0.8*len(data)):, 12]**2))
    
    # Freeze events
    freeze_events = np.sum(np.diff(data[:, 11]) > 0)
    
    # Update count
    total_updates = int(data[-1, 10])
    
    return {
        'agc_convergence_time': agc_conv_time,
        'dfe_convergence_time': dfe_conv_time,
        'cdr_lock_time': cdr_lock_time,
        'agc_steady_error': agc_steady_error,
        'dfe_steady_error': dfe_steady_error,
        'cdr_steady_error': cdr_steady_error,
        'freeze_events': freeze_events,
        'total_updates': total_updates
    }

metrics = calculate_regression_metrics(data)
print("Regression Metrics:")
for key, value in metrics.items():
    print(f"  {key}: {value}")

Regression Pass Criteria:

AGC convergence time < 5000 UI
DFE convergence time < 10000 UI
CDR lock time < 1000 UI
AGC steady-state error < 5%
DFE steady-state error < 0.001
CDR steady-state error RMS < 0.01 UI
Freeze events < 5 (normal scenarios)
Total updates meets expectations (fast path > 1000, slow path > 10)

6. Running Guide

6.1 Environment Configuration

The following environment variables need to be configured before running the Adaption testbench:

# Set SystemC library path
export SYSTEMC_HOME=/usr/local/systemc-2.3.4

# Set SystemC-AMS library path
export SYSTEMC_AMS_HOME=/usr/local/systemc-ams-2.3.4

# Or use the project-provided configuration script
source scripts/setup_env.sh

Environment Variable Descriptions:

SYSTEMC_HOME: SystemC core library installation path, contains header files and library files
SYSTEMC_AMS_HOME: SystemC-AMS extension library installation path, provides DE-TDF bridging mechanism
These paths are automatically added to compiler include and library paths through CMake

Verify Environment Configuration:

# Check if SystemC library exists
ls $SYSTEMC_HOME/lib-linux64/libsystemc-2.3.4.so

# Check if SystemC-AMS library exists
ls $SYSTEMC_AMS_HOME/lib-linux64/libsystemc-ams-2.3.4.so

# Check if CMake can find libraries
cmake .. -DCMAKE_BUILD_TYPE=Release

Common Issues:

If libsystemc-2.3.4.so is not found, check if SYSTEMC_HOME path is correct
If libsystemc-ams-2.3.4.so is not found, check if SYSTEMC_AMS_HOME path is correct
If undefined reference errors occur during linking, ensure library file paths are correct

6.2 Build and Run

Build Using CMake

# Enter project root directory
cd /mnt/d/systemCProjects/SerDesSystemCProject

# Create build directory
mkdir -p build && cd build

# Configure CMake (Release mode for best performance)
cmake .. -DCMAKE_BUILD_TYPE=Release

# Compile Adaption testbench
make adaption_tran_tb -j4

# Enter testbench directory
cd tb

CMake Configuration Options:

-DCMAKE_BUILD_TYPE=Release: Release mode, optimized performance
-DCMAKE_BUILD_TYPE=Debug: Debug mode, includes debug information
-DSYSTEMC_HOME=<path>: Specify SystemC installation path (if environment variable not set)
-DSYSTEMC_AMS_HOME=<path>: Specify SystemC-AMS installation path (if environment variable not set)

Build Output:

Executable: build/tb/adaption_tran_tb
Library file: build/lib/libserdes.a (static library)
Dependencies: SystemC, SystemC-AMS, nlohmann/json, yaml-cpp

Run Testbench

# Run Adaption testbench, specify test scenario
./adaption_tran_tb [scenario]

Scenario Parameter Descriptions:

Scenario Parameter	Value	Test Objective	Output File	Simulation Duration
`basic` / `0`	`basic` or `0`	Basic function test (all algorithms joint)	adaption_basic.csv	10 μs
`agc` / `1`	`agc` or `1`	AGC automatic gain control	adaption_agc.csv	10 μs
`dfe` / `2`	`dfe` or `2`	DFE tap update (LMS/Sign-LMS)	adaption_dfe.csv	10 μs
`threshold` / `3`	`threshold` or `3`	Threshold adaptation algorithm	adaption_threshold.csv	10 μs
`cdr_pi` / `4`	`cdr_pi` or `4`	CDR PI controller	adaption_cdr.csv	10 μs
`safety` / `5`	`safety` or `5`	Freeze and rollback mechanism	adaption_safety.csv	10 μs
`multirate` / `6`	`multirate` or `6`	Multi-rate scheduling architecture	adaption_multirate.csv	10 μs
`switch` / `7`	`switch` or `7`	Multi-scenario hot-swap	adaption_switch.csv	9 μs

Run Examples:

# Run basic function test (default scenario)
./adaption_tran_tb

# Or explicitly specify scenario
./adaption_tran_tb basic

# Run AGC test
./adaption_tran_tb agc

# Run DFE test
./adaption_tran_tb dfe

# Run freeze and rollback mechanism test
./adaption_tran_tb freeze

# Run multi-scenario hot-swap test
./adaption_tran_tb switch

Command Line Options:

If no scenario parameter is specified, default runs basic scenario
Scenario parameter can be name (e.g., basic) or number (e.g., 0)
Invalid scenario parameters will display help information

Build Using Makefile

# In project root directory
make adaption_tb

# Run test
cd build/tb
./adaption_tran_tb [scenario]

Makefile Targets:

make adaption_tb: Compile Adaption testbench
make all: Compile all modules and testbenches
make clean: Clean build artifacts
make info: Display build information

Debug Mode:

# Compile using Debug mode (includes debug symbols)
cmake .. -DCMAKE_BUILD_TYPE=Debug

# Run GDB debugging
gdb ./adaption_tran_tb

# Run Valgrind memory check
valgrind --leak-check=full ./adaption_tran_tb basic

6.3 Result Viewing

Console Output

After test run completion, the console outputs detailed statistics. The following takes basic scenario as an example:

========================================
Adaption Testbench - BASIC_FUNCTION Scenario
========================================

Simulation Configuration:
  Symbol Rate: 40 Gbps (UI = 25.00 ps)
  Simulation Duration: 10.00 μs (400,000 UI)
  Update Mode: multi-rate
  Fast Path Period: 250.00 ps (10 UI)
  Slow Path Period: 2.50 μs (100 UI)

AGC Statistics:
  Initial Gain: 2.000
  Final Gain: 3.245
  Convergence Time: 2,450 UI (61.25 ns)
  Steady-State Error: 1.2%
  Gain Adjustment Range: 1.245

DFE Statistics:
  Number of Taps: 5
  Algorithm: sign-lms
  Step Size: 1.00e-04
  Initial Taps: [-0.050, -0.020, 0.010, 0.005, 0.002]
  Final Taps: [-0.123, -0.087, 0.045, 0.023, 0.011]
  Convergence Time: 8,760 UI (219.00 ns)
  Tap Energy Distribution: 0.0256
  BER Improvement: 15.3x (BER: 5.2e-9 → 3.4e-10)

CDR PI Statistics:
  Initial Phase Error: 0.500 UI
  Lock Time: 890 UI (22.25 ns)
  Steady-State Phase Error RMS: 0.008 UI (0.20 ps)
  Phase Command Range Utilization: 45%
  Phase Jitter RMS: 0.006 UI

Threshold Adaptation Statistics:
  Initial Threshold: 0.000 V
  Final Threshold: 0.012 V
  Initial Hysteresis: 0.020 V
  Final Hysteresis: 0.025 V
  Threshold Tracking Delay: 150 UI (3.75 ns)

Safety Mechanism Statistics:
  Freeze Events: 0
  Rollback Events: 0
  Snapshot Save Count: 10

Update Statistics:
  Fast Path Updates: 40,000
  Slow Path Updates: 4,000
  Total Updates: 44,000

Overall Performance:
  Eye Opening: 62% UI (Eye Height 0.31V, Eye Width 0.62 UI)
  TJ@1e-12: 0.28 UI
  Bit Error Rate: 3.4e-10

========================================
Test Passed!
Output File: adaption_basic.csv
========================================

Console Output Descriptions:

Simulation Configuration: Displays symbol rate, simulation duration, update mode, and other basic configurations
AGC Statistics: Displays gain convergence, convergence time, steady-state error
DFE Statistics: Displays tap convergence, convergence time, BER improvement
CDR PI Statistics: Displays phase locking, lock time, steady-state phase error
Threshold Adaptation Statistics: Displays threshold adjustment, hysteresis window changes
Safety Mechanism Statistics: Displays freeze events, rollback events, snapshot save count
Update Statistics: Displays fast path/slow path update counts
Overall Performance: Displays eye opening, total jitter, bit error rate

CSV Output File Format

The CSV file generated by the testbench contains parameter time series and status signals for post-processing analysis and regression verification.

File Naming Convention:

adaption_<scenario>.csv

Where <scenario> is the test scenario name (basic, agc, dfe, threshold, cdr, freeze, multirate, switch).

Column Structure:

Column Name	Type	Unit	Description
`Time(s)`	double	seconds	Simulation timestamp
`vga_gain`	double	linear multiplier	VGA gain value
`dfe_tap1` ~ `dfe_tapN`	double	-	DFE tap coefficients (N is number of taps, usually 5-8)
`sampler_threshold`	double	V	Sampling threshold
`sampler_hysteresis`	double	V	Hysteresis window
`phase_cmd`	double	seconds	Phase command
`update_count`	int	-	Update counter
`freeze_flag`	int	-	Freeze flag (0=normal, 1=freeze)
`phase_error`	double	UI	Phase error
`amplitude_rms`	double	V	Amplitude RMS
`error_count`	int	-	Error count

Example Data:

Time(s),vga_gain,dfe_tap1,dfe_tap2,dfe_tap3,dfe_tap4,dfe_tap5,sampler_threshold,sampler_hysteresis,phase_cmd,update_count,freeze_flag,phase_error,amplitude_rms,error_count
0.000000e+00,2.000000,-0.050000,-0.020000,0.010000,0.005000,0.002000,0.000000,0.020000,0.000000,0,0,0.500000,0.250000,0
2.500000e-10,2.000000,-0.050000,-0.020000,0.010000,0.005000,0.002000,0.000000,0.020000,0.005000,1,0,0.489000,0.255000,0
5.000000e-10,2.000000,-0.050000,-0.020000,0.010000,0.005000,0.002000,0.000000,0.020000,0.010000,2,0,0.478000,0.260000,0
...
2.450000e-07,3.245000,-0.123000,-0.087000,0.045000,0.023000,0.011000,0.012000,0.025000,0.000000,2450,0,0.008000,0.398000,12
...

Data Reading Example:

import numpy as np

# Read CSV file
data = np.loadtxt('adaption_basic.csv', delimiter=',', skiprows=1)
time = data[:, 0]
vga_gain = data[:, 1]
dfe_taps = data[:, 2:7]  # Assume 5 taps
sampler_threshold = data[:, 7]
sampler_hysteresis = data[:, 8]
phase_cmd = data[:, 9]
update_count = data[:, 10]
freeze_flag = data[:, 11]
phase_error = data[:, 12]
amplitude_rms = data[:, 13]
error_count = data[:, 14]

Python Visualization

The project provides Python scripts for result visualization and analysis.

Using Project-Provided Plotting Scripts:

# Basic waveform plotting
python scripts/plot_adaption_results.py --input adaption_basic.csv

# Specify output file
python scripts/plot_adaption_results.py --input adaption_basic.csv --output my_plot.png

# Plot specific algorithm convergence curves
python scripts/plot_adaption_results.py --input adaption_agc.csv --plot-type agc
python scripts/plot_adaption_results.py --input adaption_dfe.csv --plot-type dfe
python scripts/plot_adaption_results.py --input adaption_cdr.csv --plot-type cdr

Custom Python Analysis Example:

import numpy as np
import matplotlib.pyplot as plt

# Read CSV file
data = np.loadtxt('adaption_basic.csv', delimiter=',', skiprows=1)
time = data[:, 0]
vga_gain = data[:, 1]
dfe_taps = data[:, 2:7]
sampler_threshold = data[:, 7]
phase_cmd = data[:, 9]
update_count = data[:, 10]
freeze_flag = data[:, 11]

# Plot parameter convergence curves
plt.figure(figsize=(15, 10))

# VGA gain convergence
plt.subplot(2, 3, 1)
plt.plot(time * 1e6, vga_gain)
plt.xlabel('Time (μs)')
plt.ylabel('VGA Gain')
plt.title('AGC Gain Convergence')
plt.grid(True)

# DFE tap convergence
plt.subplot(2, 3, 2)
for i in range(dfe_taps.shape[1]):
    plt.plot(time * 1e6, dfe_taps[:, i], label=f'Tap {i+1}')
plt.xlabel('Time (μs)')
plt.ylabel('Tap Coefficient')
plt.title('DFE Tap Convergence')
plt.legend()
plt.grid(True)

# Phase command
plt.subplot(2, 3, 3)
plt.plot(time * 1e6, phase_cmd * 1e12)
plt.xlabel('Time (μs)')
plt.ylabel('Phase Command (ps)')
plt.title('CDR Phase Command')
plt.grid(True)

# Phase error
plt.subplot(2, 3, 4)
plt.plot(time * 1e6, phase_error)
plt.xlabel('Time (μs)')
plt.ylabel('Phase Error (UI)')
plt.title('CDR Phase Error')
plt.grid(True)

# Freeze flag
plt.subplot(2, 3, 5)
plt.plot(time * 1e6, freeze_flag)
plt.xlabel('Time (μs)')
plt.ylabel('Freeze Flag')
plt.title('Freeze Status')
plt.grid(True)

# Update count
plt.subplot(2, 3, 6)
plt.plot(time * 1e6, update_count)
plt.xlabel('Time (μs)')
plt.ylabel('Update Count')
plt.title('Update Counter')
plt.grid(True)

plt.tight_layout()
plt.savefig('adaption_convergence.png', dpi=300)
plt.show()

Convergence Analysis Example:

# Calculate AGC convergence time (gain change < 1% for 10 consecutive updates)
gain_change = np.abs(np.diff(vga_gain)) / vga_gain[:-1]
converged_indices = np.where(gain_change < 0.01)[0]
if len(converged_indices) > 0:
    # Check if sustained for 10 consecutive updates
    for i in range(len(converged_indices) - 10):
        if np.all(gain_change[converged_indices[i]:converged_indices[i]+10] < 0.01):
            agc_convergence_time = time[converged_indices[i]]
            print(f"AGC Convergence Time: {agc_convergence_time * 1e6:.2f} μs ({agc_convergence_time / 2.5e-11:.0f} UI)")
            break

# Calculate DFE convergence time (all tap changes < 0.001 for 10 consecutive updates)
dfe_converged = False
for i in range(len(dfe_taps) - 10):
    tap_changes = np.abs(np.diff(dfe_taps[i:i+10], axis=0))
    if np.all(tap_changes < 0.001):
        dfe_convergence_time = time[i]
        print(f"DFE Convergence Time: {dfe_convergence_time * 1e6:.2f} μs ({dfe_convergence_time / 2.5e-11:.0f} UI)")
        dfe_converged = True
        break

if not dfe_converged:
    print("DFE taps not fully converged")

# Calculate CDR lock time (phase error < 0.01 UI for 100 consecutive updates)
locked_indices = np.where(np.abs(phase_error) < 0.01)[0]
if len(locked_indices) > 100:
    for i in range(len(locked_indices) - 100):
        if np.all(np.abs(phase_error[locked_indices[i]:locked_indices[i]+100]) < 0.01):
            cdr_lock_time = time[locked_indices[i]]
            print(f"CDR Lock Time: {cdr_lock_time * 1e6:.2f} μs ({cdr_lock_time / 2.5e-11:.0f} UI)")
            break

# Count freeze events
freeze_events = np.sum(np.diff(freeze_flag) > 0)
print(f"Freeze Events: {freeze_events}")

Regression Verification Example:

# Calculate regression metrics
def calculate_regression_metrics(data):
    # Convergence time
    agc_conv_time = calculate_convergence_time(data[:, 1], threshold=0.01)
    dfe_conv_time = calculate_dfe_convergence_time(data[:, 2:7], threshold=0.001)
    cdr_lock_time = calculate_lock_time(data[:, 12], threshold=0.01)
    
    # Steady-state error
    agc_steady_error = calculate_steady_error(data[:, 1], start_idx=int(0.8*len(data)))
    dfe_steady_error = calculate_dfe_steady_error(data[:, 2:7], start_idx=int(0.8*len(data)))
    cdr_steady_error = np.sqrt(np.mean(data[int(0.8*len(data)):, 12]**2))
    
    # Freeze events
    freeze_events = np.sum(np.diff(data[:, 11]) > 0)
    
    # Update count
    total_updates = int(data[-1, 10])
    
    return {
        'agc_convergence_time': agc_conv_time,
        'dfe_convergence_time': dfe_conv_time,
        'cdr_lock_time': cdr_lock_time,
        'agc_steady_error': agc_steady_error,
        'dfe_steady_error': dfe_steady_error,
        'cdr_steady_error': cdr_steady_error,
        'freeze_events': freeze_events,
        'total_updates': total_updates
    }

metrics = calculate_regression_metrics(data)
print("Regression Metrics:")
for key, value in metrics.items():
    print(f"  {key}: {value}")

# Regression pass criteria
print("\nRegression Verification:")
print(f"  AGC Convergence Time < 5000 UI: {'✓' if metrics['agc_convergence_time'] / 2.5e-11 < 5000 else '✗'}")
print(f"  DFE Convergence Time < 10000 UI: {'✓' if metrics['dfe_convergence_time'] / 2.5e-11 < 10000 else '✗'}")
print(f"  CDR Lock Time < 1000 UI: {'✓' if metrics['cdr_lock_time'] / 2.5e-11 < 1000 else '✗'}")
print(f"  AGC Steady-State Error < 5%: {'✓' if metrics['agc_steady_error'] < 0.05 else '✗'}")
print(f"  DFE Steady-State Error < 0.001: {'✓' if metrics['dfe_steady_error'] < 0.001 else '✗'}")
print(f"  CDR Steady-State Error RMS < 0.01 UI: {'✓' if metrics['cdr_steady_error'] < 0.01 else '✗'}")
print(f"  Freeze Events < 5: {'✓' if metrics['freeze_events'] < 5 else '✗'}")
print(f"  Fast Path Updates > 1000: {'✓' if metrics['total_updates'] > 1000 else '✗'}")

Multi-Scenario Comparison Analysis:

import glob
import os

# Read CSV files for all scenarios
scenarios = ['basic', 'agc', 'dfe', 'threshold', 'cdr', 'freeze', 'multirate', 'switch']
results = {}

for scenario in scenarios:
    csv_file = f'adaption_{scenario}.csv'
    if os.path.exists(csv_file):
        data = np.loadtxt(csv_file, delimiter=',', skiprows=1)
        results[scenario] = calculate_regression_metrics(data)

# Comparison analysis
print("Multi-Scenario Comparison Analysis:")
print(f"{'Scenario':<15} {'AGC Conv Time(ns)':<18} {'DFE Conv Time(ns)':<18} {'CDR Lock Time(ns)':<18} {'Freeze Events':<13}")
print("-" * 82)
for scenario, metrics in results.items():
    agc_conv = metrics['agc_convergence_time'] * 1e9 if 'agc_convergence_time' in metrics else 'N/A'
    dfe_conv = metrics['dfe_convergence_time'] * 1e9 if 'dfe_convergence_time' in metrics else 'N/A'
    cdr_lock = metrics['cdr_lock_time'] * 1e9 if 'cdr_lock_time' in metrics else 'N/A'
    freeze = metrics['freeze_events'] if 'freeze_events' in metrics else 'N/A'
    print(f"{scenario:<15} {str(agc_conv):<18} {str(dfe_conv):<18} {str(cdr_lock):<18} {str(freeze):<13}")

Performance Analysis Script:

# Calculate performance metrics
def calculate_performance_metrics(data):
    # Eye opening (assuming eye diagram data available)
    # eye_height = ...
    # eye_width = ...
    # eye_area = eye_height * eye_width
    
    # Jitter decomposition
    tj = np.percentile(np.abs(phase_error), 99.9999999)  # TJ@1e-12
    rj = np.std(phase_error)  # RJ
    dj = tj - rj  # DJ
    
    # Bit error rate
    ber = error_count[-1] / (len(time) * 40e9 * 2.5e-11)  # Rough estimate
    
    return {
        'tj': tj,
        'rj': rj,
        'dj': dj,
        'ber': ber
    }

perf_metrics = calculate_performance_metrics(data)
print("Performance Metrics:")
print(f"  TJ@1e-12: {perf_metrics['tj']:.4f} UI")
print(f"  RJ: {perf_metrics['rj']:.4f} UI")
print(f"  DJ: {perf_metrics['dj']:.4f} UI")
print(f"  BER: {perf_metrics['ber']:.2e}")

Batch Test Script:

#!/bin/bash
# Batch run all test scenarios

SCENARIOS=("basic" "agc" "dfe" "threshold" "cdr" "freeze" "multirate" "switch")

for scenario in "${SCENARIOS[@]}"; do
    echo "Running scenario: $scenario"
    ./adaption_tran_tb "$scenario"
    if [ $? -eq 0 ]; then
        echo "✓ Scenario $scenario test passed"
    else
        echo "✗ Scenario $scenario test failed"
    fi
    echo ""
done

# Generate regression report
python scripts/generate_regression_report.py

Output File Descriptions:

adaption_<scenario>.csv: Parameter time series data
adaption_convergence.png: Parameter convergence curves
adaption_analysis.png: Comprehensive analysis plots
regression_report.txt: Regression verification report

Python Analysis Example:

import numpy as np
import matplotlib.pyplot as plt

# Read CSV file
data = np.loadtxt('adaption_basic.csv', delimiter=',', skiprows=1)
time = data[:, 0]
vga_gain = data[:, 1]
dfe_taps = data[:, 2:7]
sampler_threshold = data[:, 7]
phase_cmd = data[:, 9]
update_count = data[:, 10]
freeze_flag = data[:, 11]

# Plot VGA gain convergence curve
plt.figure(figsize=(12, 8))

plt.subplot(2, 2, 1)
plt.plot(time * 1e6, vga_gain)
plt.xlabel('Time (μs)')
plt.ylabel('VGA Gain')
plt.title('AGC Gain Convergence')
plt.grid(True)

# Plot DFE tap convergence curves
plt.subplot(2, 2, 2)
for i in range(5):
    plt.plot(time * 1e6, dfe_taps[:, i], label=f'Tap {i+1}')
plt.xlabel('Time (μs)')
plt.ylabel('Tap Coefficient')
plt.title('DFE Tap Convergence')
plt.legend()
plt.grid(True)

# Plot phase command curve
plt.subplot(2, 2, 3)
plt.plot(time * 1e6, phase_cmd * 1e12)
plt.xlabel('Time (μs)')
plt.ylabel('Phase Command (ps)')
plt.title('CDR Phase Command')
plt.grid(True)

# Plot freeze flag
plt.subplot(2, 2, 4)
plt.plot(time * 1e6, freeze_flag)
plt.xlabel('Time (μs)')
plt.ylabel('Freeze Flag')
plt.title('Freeze Status')
plt.grid(True)

plt.tight_layout()
plt.savefig('adaption_analysis.png', dpi=300)
plt.show()

Performance Analysis

Calculate convergence time and steady-state error:

# Calculate AGC convergence time (gain change < 1%)
gain_stable_idx = np.where(np.abs(np.diff(vga_gain)) / vga_gain[:-1] < 0.01)[0]
if len(gain_stable_idx) > 0:
    agc_convergence_time = time[gain_stable_idx[0]]
    print(f"AGC Convergence Time: {agc_convergence_time * 1e6:.2f} μs")

# Calculate DFE convergence time (tap change < 0.001)
tap_stable = True
for i in range(5):
    tap_stable_idx = np.where(np.abs(np.diff(dfe_taps[:, i])) < 0.001)[0]
    if len(tap_stable_idx) > 0:
        tap_stable = tap_stable and (len(tap_stable_idx) > len(time) * 0.9)

if tap_stable:
    print("DFE taps converged")
else:
    print("DFE taps not fully converged")

# Count freeze events
freeze_events = np.sum(np.diff(freeze_flag) > 0)
print(f"Freeze Events: {freeze_events}")

7. Technical Essentials

7.1 DE-TDF Bridge Timing Alignment and Delay Handling

Problem: There is cross-domain communication delay between DE domain control logic and TDF domain analog front-end, which may cause parameter update and signal processing timing misalignment, affecting control loop stability.

Solutions:

DE→TDF bridge has 1 TDF cycle inherent delay, parameters take effect in the next TDF sampling cycle after DE event completion
Compensate delay impact by reducing update frequency: fast path updates every 10-100 UI, slow path updates every 1000-10000 UI
PI controller's integral coefficient Ki is appropriately reduced to increase stability margin
When multiple parameters update simultaneously, SystemC-AMS bridging mechanism guarantees atomicity, TDF modules read all new parameters in the same sampling cycle
After scenario switch, enter brief training period (usually 100-200 UI), freeze error statistics, avoid transient false triggering of freeze/rollback

Implementation Points:

// Fast path update period should be much larger than TDF time step to avoid races
fast_update_period = 10 * UI;  // 10 UI ≈ 250ps @ 40Gbps
slow_update_period = 1000 * UI;  // 1000 UI ≈ 25ns @ 40Gbps

7.2 Multi-Rate Scheduling Architecture Implementation Details

Problem: The four major adaptive algorithms (AGC, DFE, Threshold, CDR PI) have different update frequency requirements, single-rate scheduling leads to computational waste or insufficient response.

Solutions:

Adopt hierarchical multi-rate architecture: fast path (CDR PI, threshold adaptation, every 10-100 UI) and slow path (AGC, DFE taps, every 1000-10000 UI) run in parallel
Use SystemC DE domain event triggers, create timed events for fast/slow paths separately
Fast path has higher priority than slow path, avoiding slow path blocking fast path response
Update counters separately count fast/slow path updates for diagnostics and performance analysis

Implementation Points:

// Fast path timed event
sc_core::sc_event fast_update_event;
next_fast_trigger = current_time + fast_update_period;
next_fast_trigger.notify(fast_update_period);

// Slow path timed event
sc_core::sc_event slow_update_event;
next_slow_trigger = current_time + slow_update_period;
next_slow_trigger.notify(slow_update_period);

7.3 AGC PI Controller Convergence and Stability

Problem: AGC PI controller needs to quickly respond to amplitude changes while avoiding gain oscillation and overshoot, ensuring small steady-state error.

Solutions:

Proportional coefficient Kp controls response speed, integral coefficient Ki eliminates steady-state error, typical values Kp=0.01-0.1, Ki=10-1000
Gain range clamped to [gain_min, gain_max], preventing signal loss from too small gain or saturation from too large gain
Rate limit rate_limit prevents excessive gain change in single update, typical value 10.0 linear/s
Anti-windup strategy: when gain exceeds range, stop integral term accumulation, avoiding integrator overflow

Convergence Determination Criteria:

Gain change rate < 1% for 10 consecutive updates
Amplitude tracking error < 5%
Convergence time < 5000 UI

7.4 DFE Sign-LMS Algorithm Convergence and Stability

Problem: DFE tap updates need to balance fast convergence and steady-state accuracy, preventing noise accumulation causing tap divergence.

Solutions:

Default uses Sign-LMS algorithm, only requires addition operations, hardware-friendly and robust
Step size mu adjusted based on signal power and noise, typical value 1e-5 - 1e-3, satisfying stability condition 0 < μ < 2 / (N * P_x)
Leakage coefficient leakage (1e-6 - 1e-4) prevents noise accumulation causing tap divergence, applied as tap[i] *= (1 - leakage) after each update
Tap saturation clamped to [tap_min, tap_max], preventing tap coefficients from being too large or too small
Freeze condition: If decision error |e(n)| > freeze_threshold, pause all tap updates, avoiding abnormal noise interference

Convergence Determination Criteria:

All tap changes < 0.001 for 10 consecutive updates
BER improvement > 10x (vs no DFE)
Convergence time < 10000 UI
No divergence during long-term operation (1e6 UI)

7.5 Threshold Adaptation Algorithm Robustness Design

Problem: Threshold adaptation needs to track level drift while avoiding extreme threshold triggering during abnormal noise surges.

Solutions:

Use gradient descent or level statistics method to adjust threshold, moving toward direction of decreasing errors
Threshold adjustment step adapt_step limits single update amplitude, typical value 0.001V
Level drift threshold drift_threshold (e.g., 0.05V) triggers threshold adjustment when exceeded, avoiding frequent fine-tuning
Hysteresis window dynamically adjusts based on noise intensity: hysteresis = k * σ_noise, where k is coefficient (2-3), limited to [0.01, 0.1] range
During abnormal noise surges, freeze threshold updates, maintain current value

Robustness Verification:

Threshold tracking error < 10mV
Hysteresis window adaptive adjustment, balancing noise immunity and sensitivity
No extreme threshold triggering during abnormal noise surges

7.6 CDR PI Controller Anti-Windup Handling

Problem: Under large phase disturbance, CDR PI controller's integrator may accumulate too much causing phase command overflow, affecting lock performance.

Solutions:

Phase command range clamped to ±phase_range, typically 5e-11 seconds (±0.5 UI)
Anti-windup strategy: when phase command exceeds range, clamp and stop integral term accumulation

if (phase_cmd > phase_range) {
    phase_cmd = phase_range;
    // Stop integral accumulation, avoid integrator overflow
} else if (phase_cmd < -phase_range) {
    phase_cmd = -phase_range;
    // Stop integral accumulation
} else {
    I_cdr += ki_cdr * phase_error * dt;
}

Phase command quantized by phase_resolution, matching phase interpolator's actual resolution
Reduce integral coefficient Ki after locking, improving steady-state jitter suppression capability

Lock Determination Criteria:

Phase error RMS < 0.01 UI for 100 consecutive updates
Lock time < 1000 UI
Phase jitter RMS < 0.01 UI

7.7 Safety Mechanism Trigger Conditions and Recovery Strategy

Problem: Under abnormal scenarios (signal loss, noise surge, configuration error), algorithms may diverge, requiring freeze updates and quick recovery.

Solutions:

Freeze Trigger Conditions:
- Error burst: error_count > error_burst_threshold
- Amplitude anomaly: amplitude_rms outside [target_amplitude * 0.5, target_amplitude * 2.0]
- Phase unlock: |phase_error| > 5e-11 (0.5 UI) for more than 1000 UI
Snapshot Save: Save current parameters to history buffer every snapshot_interval (e.g., 1 μs)
Rollback Trigger: Freeze duration exceeds threshold (e.g., 2 * snapshot_interval) or key metrics continue to degrade
Recovery Strategy: Restore parameters from snapshot buffer, reset integrator, clear freeze flag, enter training mode

Recovery Determination Criteria:

Recovery time < 2000 UI
Parameters converge to stable values after recovery
Freeze/rollback events < 5 times (normal scenarios)

7.8 Parameter Constraints and Clamping Design

Problem: All output parameters must be within reasonable ranges, preventing parameter divergence causing system instability.

Solutions:

AGC Gain: gain = clamp(gain, gain_min, gain_max), typical range [0.5, 8.0]
DFE Taps: tap[i] = clamp(tap[i], tap_min, tap_max), typical range [-0.5, 0.5]
Threshold: threshold = clamp(threshold, -vcm_out, vcm_out), preventing exceeding common-mode voltage range
Phase Command: phase_cmd = clamp(phase_cmd, -phase_range, phase_range), typical range 5e-11 seconds (±0.5 UI)
Rate Limit: AGC gain change rate limit rate_limit, preventing gain突变

Implementation Points:

template<typename T>
T clamp(T value, T min_val, T max_val) {
    return (value < min_val) ? min_val : (value > max_val) ? max_val : value;
}

7.9 Scenario Switching Atomicity and Anti-Shake Strategy

Problem: During multi-scenario hot-swap, parameter inconsistency may cause transient errors, affecting system stability.

Solutions:

Atomic Switching: All parameters (vga_gain, dfe_taps, sampler_threshold, phase_cmd) update simultaneously within the same DE event
Anti-Shake Strategy: After switch, enter brief training period (usually 100-200 UI), freeze error statistics, avoid transient false triggering of freeze/rollback
Snapshot Save: Save current parameter snapshot before switching, facilitating fault recovery
Mode Control: Control switching flow through mode signal (0=initialization, 1=training, 2=data, 3=freeze)

Switch Determination Criteria:

Switch time < 100 UI
No transient errors due to parameter inconsistency
Switch success rate 100%

7.10 Known Limitations and Special Requirements

Limitation 1: DE-TDF Bridge Delay

DE→TDF bridge has 1 TDF cycle inherent delay, cannot be avoided
Algorithm design needs to consider this delay's impact on stability, compensated by reducing update frequency and increasing damping coefficient

Limitation 2: Sign-LMS Algorithm Steady-State Error

Sign-LMS algorithm's steady-state error is larger than LMS algorithm
Can be compensated through leakage mechanism and freeze threshold, or switch to LMS/NLMS algorithm

Limitation 3: Multi-Rate Scheduling Overhead

High fast path update frequency may increase computational overhead
Can be optimized by dynamically adjusting update frequency, e.g., use fast update during training phase, slow update during data phase

Special Requirement 1: Simulation Time

Under PSRR/CMRR test scenarios, simulation time must be no less than 3 μs, ensuring complete coverage of at least 3 cycles of 1 MHz signal changes
Under DFE convergence test scenarios, simulation time must be no less than 10 μs, ensuring sufficient tap convergence

Special Requirement 2: Port Connections

All input ports must be connected, even if corresponding algorithm is not enabled (SystemC-AMS requirement)
Recommended to connect to default values or zero signals to avoid undefined behavior

Special Requirement 3: Configuration Completeness

Configuration files must contain all algorithm parameters, missing parameters will cause loading failure
Recommended to use configuration validation tools to ensure parameter range compliance

8. Reference Information

8.1 Related Files

File	Path	Description
Parameter Definition	`/include/common/parameters.h`	AdaptionParams structure (contains AGC, DFE, Threshold, CDR PI, Safety and Rollback sub-structures)
Header File	`/include/de/adaption.h`	AdaptionDe class declaration (DE domain adaptive control hub)
Implementation File	`/src/de/adaption.cpp`	AdaptionDe class implementation (four major algorithms and multi-rate scheduling)
Testbench	`/tb/adaption/adaption_tran_tb.cpp`	Transient simulation test (eight test scenarios)
Test Helpers	`/tb/adaption/adaption_helpers.h`	Helper modules (TraceMonitor, FaultInjector, ScenarioManager)
Unit Test	`/tests/unit/test_adaption_basic.cpp`	GoogleTest unit tests (AGC, DFE, Threshold, CDR PI)
Config File	`/config/default.json`	Default configuration (JSON format)
Config File	`/config/default.yaml`	Default configuration (YAML format)
Waveform Plotting	`/scripts/plot_adaption_results.py`	Python visualization script (convergence curves, eye diagram comparison)

8.2 Dependencies

SystemC 2.3.4 (DE domain simulation core)
SystemC-AMS 2.3.4 (DE-TDF bridging mechanism)
C++11/C++14 standard (smart pointers, lambda expressions, chrono library)
nlohmann/json (JSON configuration parsing, version 3.11+)
yaml-cpp (YAML configuration parsing, optional, version 0.7+)
GoogleTest 1.12.1 (unit test framework)

8.3 Configuration Example

Complete configuration example (JSON format):

{
  "global": {
    "Fs": 80e9,
    "UI": 2.5e-11,
    "seed": 12345,
    "update_mode": "multi-rate",
    "fast_update_period": 2.5e-10,
    "slow_update_period": 2.5e-7
  },
  "adaption": {
    "agc": {
      "enabled": true,
      "target_amplitude": 0.4,
      "kp": 0.1,
      "ki": 100.0,
      "gain_min": 0.5,
      "gain_max": 8.0,
      "rate_limit": 10.0,
      "initial_gain": 2.0
    },
    "dfe": {
      "enabled": true,
      "num_taps": 5,
      "algorithm": "sign-lms",
      "mu": 1e-4,
      "leakage": 1e-6,
      "initial_taps": [-0.05, -0.02, 0.01, 0.005, 0.002],
      "tap_min": -0.5,
      "tap_max": 0.5,
      "freeze_threshold": 0.1
    },
    "threshold": {
      "enabled": true,
      "initial": 0.0,
      "hysteresis": 0.02,
      "adapt_step": 0.001,
      "target_ber": 1e-9,
      "drift_threshold": 0.05
    },
    "cdr_pi": {
      "enabled": true,
      "kp": 0.01,
      "ki": 1e-4,
      "phase_resolution": 1e-12,
      "phase_range": 5e-11,
      "anti_windup": true,
      "initial_phase": 0.0
    },
    "safety": {
      "freeze_on_error": true,
      "rollback_enable": true,
      "snapshot_interval": 1e-6,
      "error_burst_threshold": 100
    }
  }
}

Document Version: v0.1
Last Updated: 2025-10-30
Author: Yizhe Liu

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Adaption Module Technical Documentation

1. Overview

1.1 Design Principles

1.2 Core Features

1.3 Version History

2. Module Interface

2.1 Port Definitions (DE Domain)

Input Ports (from RX/CDR/SystemConfiguration)

Output Ports (to RX/CDR)

Bridge Mechanism Description

2.2 Parameter Configuration (AdaptionParams)

Basic Parameters

AGC Sub-Structure

DFE Sub-Structure

Threshold Adaptation Sub-Structure

CDR PI Sub-Structure

Safety and Rollback Sub-Structure

4. Testbench Architecture

4.1 Testbench Design Philosophy

4.2 Test Scenario Definitions

4.3 Scenario Configuration Details

BASIC_FUNCTION - Basic Function Test

AGC_TEST - AGC Automatic Gain Control Test

DFE_TEST - DFE Tap Update Test

THRESHOLD_TEST - Threshold Adaptation Test

CDR_PI_TEST - CDR PI Controller Test

FREEZE_ROLLBACK - Freeze and Rollback Mechanism Test

MULTI_RATE - Multi-Rate Scheduling Architecture Test

SCENARIO_SWITCH - Multi-Scenario Hot-Swap Test

4.4 Signal Connection Topology

4.5 Auxiliary Module Descriptions

WaveGen - Waveform Generator

Channel - Channel Model

RX Link - Receiver Link

CDR - Clock Data Recovery

TraceMonitor - Trace Monitor

FaultInjector - Fault Injector

ScenarioManager - Scenario Manager

5. Simulation Results Analysis

5.1 Statistical Metrics Description

5.1.1 Convergence Metrics

5.1.2 Performance Metrics

5.1.3 System Metrics

5.1.4 Algorithm-Specific Metrics

5.2 Typical Test Result Interpretation

5.2.1 BASIC_FUNCTION Scenario

5.2.2 AGC_TEST Scenario

5.2.3 DFE_TEST Scenario

5.2.4 FREEZE_ROLLBACK Scenario

5.2.5 MULTI_RATE Scenario

5.2.6 THRESHOLD_TEST Scenario

5.2.7 CDR_PI_TEST Scenario

5.2.8 SCENARIO_SWITCH Scenario

5.3 Waveform Data File Format

5.3.1 CSV File Format

5.3.2 Data Reading and Processing

5.3.3 Convergence Analysis

5.3.4 Visualization Example

5.3.5 Regression Verification

6. Running Guide

6.1 Environment Configuration

6.2 Build and Run

Build Using CMake

Run Testbench

Build Using Makefile

6.3 Result Viewing

Console Output

CSV Output File Format

Python Visualization

Performance Analysis

7. Technical Essentials

7.1 DE-TDF Bridge Timing Alignment and Delay Handling

7.2 Multi-Rate Scheduling Architecture Implementation Details

7.3 AGC PI Controller Convergence and Stability