UNIVERSITY OF WEST ATTICA
SCHOOL OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING AND INFORMATICS
University of West Attica · Department of Computer Engineering and Informatics
Logic Design
Vasileios Evangelos Athanasiou
Student ID: 19390005
Supervision
Supervisor: Konstantinos Efstathiou, Professor
Supervisor: Ioannis Amorginos, Applications Lecturer
Co-supervisor: Eleni Tsalera, Academic Scholar
Co-supervisor: Anastasios Tsilikounas, Laboratory Teaching Staff
Athens, April 2021
This README provides an overview of the Digital Design Workshop 1 report submitted to the University of West Attica. The project focuses on the theoretical study, simulation, and implementation of fundamental logic gates.
| Section | Folder/File | Description |
|---|---|---|
| 1 | assign/ |
Assignment material for the Logic Gates workshop |
| 1.1 | assign/ASSIGNMENT 1.pdf |
Assignment description in English |
| 1.2 | assign/ΕΡΓΑΣΙΑ 1.pdf |
Assignment description in Greek |
| 2 | docs/ |
Documentation covering logic gates theory and implementations |
| 2.1 | docs/Logic-Gates.pdf |
English documentation for logic gates |
| 2.2 | docs/Λογικές-Πύλες.pdf |
Greek documentation for logic gates |
| 3 | multisim/ |
Multisim logic gate simulation files |
| 3.1 | multisim/AND.ms14 |
AND gate simulation |
| 3.2 | multisim/NAND.ms14 |
NAND gate simulation |
| 3.3 | multisim/NOR.ms14 |
NOR gate simulation |
| 3.4 | multisim/NOT.ms14 |
NOT gate simulation |
| 3.5 | multisim/OR.ms14 |
OR gate simulation |
| 3.6 | multisim/propagationDelay.ms14 |
Propagation delay demonstration circuit |
| 3.7 | multisim/XNOR.ms14 |
XNOR gate simulation |
| 3.8 | multisim/XOR.ms14 |
XOR gate simulation |
| 4 | README.md |
Project documentation |
| 5 | INSTALL.md |
Usage instructions |
- Institution: University of West Attica
- Department: Information and Computer Engineering
- Course: Digital Design – Workshop 1
- Student: Athanasiou Vasileios Evangelos
- Tools Used: Multisim simulator for circuit design and analysis
The main goal of this work is to demonstrate the operation of various logic gates using:
- Truth tables
- Logical equations
- Simulated implementations
The report covers:
- Basic Gates: AND, OR, NOT
- Universal Gates: NAND, NOR
- Exclusive Gates: XOR, XNOR
- Advanced Analysis: Propagation delay measurement using four AND gates connected in series with a 100 kHz square pulse.
| Gate | Logic Equation | Behavior Summary |
|---|---|---|
| AND | F = A · B | Output is high only when both inputs are high. |
| OR | F = A + B | Output is high if at least one input is high. |
| NAND | F = ¬(A · B) | Inverted AND; output is low only when both inputs are high. |
| NOR | F = ¬(A + B) | Inverted OR; output is high only when both inputs are low. |
| XOR | F = A ⊕ B | Output is high only when inputs differ. |
| XNOR | F = ¬(A ⊕ B) | Output is high when inputs are equal. |
The simulation environment uses the following components:
- Logic "1": Represented by VCC source (5V)
- Logic "0": Represented by Ground (0V)
- Lamps (2.5V) are used to indicate input and output states.
- A lit lamp represents logic 1.
- Switches S1 and S2 toggle inputs between VCC and Ground.
- Chapter 1: Introduction and basic gate operation
- Chapter 2: Bibliography and references
- Chapter 3: Multisim implementation and components description
- Chapter 4: Exercises including truth tables, simulations, and propagation delay analysis
This workshop establishes a foundation in digital electronics by demonstrating how logic gates operate and how they can be analyzed through simulation, forming the basis for more advanced digital circuit design.