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Copy file name to clipboardExpand all lines: MemoryManager.Core/MemoryCanary.cs
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* PROGRAMMER: Peter Geinitz (Wayfarer)
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*/
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usingSystem;
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usingSystem.Runtime.CompilerServices;
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namespaceMemoryManager.Core
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/// Canary class provides a simple mechanism for detecting buffer overruns and underruns in debug builds by placing known "canary" values before and after user allocations.
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/// In release builds, the canary logic is completely stripped out to ensure zero overhead,
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/// making it an effective tool for catching memory corruption issues during development without impacting performance in production.
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/// It additionally acts as an alignment boundary engine, snapping unmanaged pointers cleanly to hardware memory channels.
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/// </summary>
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publicstaticclassMemoryCanary
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{
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/// <summary>
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/// The byte alignment requirement boundary (Must be a power of two, e.g., 16, 32, 64)
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/// </summary>
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privateconstintAlignment=16;
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/// <summary>
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/// The size
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/// </summary>
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/// </summary>
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privateconstuintMagic=0xDEADBEEF;
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/// <summary>
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/// Pre-calculated front window padding size required to fit the pre-canary and maintain power-of-two alignment
Copy file name to clipboardExpand all lines: README.md
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***Current State:** When compaction triggers, the compactor engine allocates an entirely new unmanaged heap block via `Marshal.AllocHGlobal` and slides all survivors over via memory block copying. For massive heaps (e.g., 512MB+), this causes noticeable block stutters (latency spikes) and temporarily forces a **double memory footprint**.
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***Production Fix:** Implement an **Incremental/Phased Compactor** that only relocates a small chunk of fragmented blocks per frame tick, or enforce strict zero-compaction rules where arenas are completely cleared and cycled out at deterministic boundaries (e.g., scene changes).
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### 3. Hardware Memory Alignment Blindness
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***Current State:** The bump allocators currently increment layouts directly by byte size (`_nextFreeOffset += size`). If a user allocates an odd structural layout (e.g., a 7-byte struct), subsequent items are placed on unaligned memory addresses, causing the CPU to fetch multiple cache-lines for single read instructions, tanking cache line efficiency.
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***Production Fix:** Force all lane offsets to snap cleanly to hardware alignment boundaries (e.g., 16-byte, 32-byte, or 64-byte boundaries for SIMD alignment) using power-of-two bitwise masking layout constraints:
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