FP4 (Float4E2M1) browser backends (WGSL/GLSL/Wasm) + host scalar-param fix - FP4 now on ALL 6 backends - 4.14.0-local.5

Completes Float4E2M1 (OCP E2M1FN, the NVFP4/MXFP4 element format) across every backend. The
convert/decode is now BIT-EXACT to ml_dtypes.float4_e2m1fn on CPU, CUDA, OpenCL, WebGPU, WebGL,
and Wasm. Four-package bundle: forks 2.0.31 -> 2.0.32, SpawnDev.ILGPU 4.14.0-local.4 -> local.5.

Browser convert codegen (mirrors the FP8 WGSL/GLSL/Wasm paths; the _e2m1<->f32 helpers are
line-for-line ports of the CPU/OpenCL/CUDA-verified managed conversion, byte-identical across all 6):
- WebGPU/WGSL: _e2m1_to_f32 / _f32_to_e2m1 in WGSLEmulationLibrary (minimal-trim gated) + type map
  (f32) + FloatAsInt/IntAsFloat + const + every sub-word classification/scalar/load/store/LEA site.
- WebGL/GLSL: _e2m1_to_f32 / _f32_to_e2m1 in GLSLEmulationLibrary + type map + FloatAsInt/IntAsFloat
  + const + body-struct/param/load(texelFetch)/store(TF) sites.
- Wasm: EmitFP4ToF32 / EmitF32ToFP4 inline bytecode + load (i32.load8_u) / store (i32.store8) /
  const + the struct-wrapper mis-lowering store guard.

Host sub-word SCALAR-param fix (Rule 2a - this was a latent FP8 gap too; FP8 only had buffer
round-trip tests, never a scalar-param test):
- A by-value 1-byte float scalar (scale/bias in the generic relu kernel) fell through the host
  scalar marshaling with no FP8/FP4 case: Wasm struct-serialized it (kernel read garbage -> "got 2"),
  WebGL never sent the uniform (arrived as 0). Added FP8 (E4M3/E5M2) + FP4 to the host widen-to-f32
  path next to Half/bf16 in WasmAccelerator + WebGLAccelerator (the f32-register model; the scalar
  param is declared f32/float on these backends, so pass the widened value, lossless).

Capability + tests:
- AcceleratorRequirements.RequiresFloat4E2M1 + HasFloat4() (always-true no-op filter like bf16/FP8).
- PMT BackendTestBase.GenericPrecision: PrecisionConvert_Float4E2M1_RoundTripBitExact,
  GenericPrecision_Float4E2M1_RunsAndMatchesCpu (FP4-exact scale=1.5/bias=0.5 scalar params),
  Float4E2M1_FloatToFP4_RneSaturateNaN (decode/overflow/NaN bit-exact vs managed).
- AcceleratorRequirementsTests.Satisfies_LowPrecisionFloats extended with FP4.

Gates: PMT Float4E2M1 23/0 ALL 6 backends; GenericPrecision (Half/bf16/FP4 scalar relu) 30/0;
AcceleratorRequirements 19/0/1; no regression (PrecisionConvert_Float8 16/0, desktop fp8-verify
257/257 + fp4-verify CPU/OpenCL/CUDA bit-exact, bf16-f16-oracle 65536/65536). NEXT (separate
commit): FP4 radix-sort keys, then INT4, then MXFP4/NF4 dequant.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

Author: LostBeard

CHANGELOG.md

@@ -2,6 +2,15 @@
 
 This file tracks notable changes per release. The README's "Recent Highlights" section links here for the full version history.
 
+## 4.14.0-local.5 (2026-06-17) - New 4-bit float type `Float4E2M1` (NVFP4/MXFP4 element format) on all 6 backends + a latent low-precision store-widening bug fix
+
+Adds `ILGPU.Float4E2M1`, the OCP **E2M1FN** 4-bit float (the element format of NVFP4 / MXFP4): 1 sign / 2 exp / 1 mantissa, bias 1, **16 finite codes (no Inf, no NaN)**, magnitudes `{0,.5,1,1.5,2,3,4,6}`, max 6, finite overflow + ±Inf saturate to ±6, NaN→-0. 1-byte storage (value in the low nibble), f32-register compute. Forks bump to `2.0.32`. Bit-exact to `ml_dtypes.float4_e2m1fn` (PyTorch/JAX share it).
+
+- **First-class IR primitive on all 6 backends** (CPU, CUDA, OpenCL, WebGPU, WebGL, Wasm), mirroring the FP8 wiring: `BasicValueType.Float4E2M1` + `ArithmeticBasicValueType.Float4E2M1` (appended at the end - all existing ordinals + positional type tables unchanged), `INumber<Float4E2M1>` (E2M1 has neither Inf nor NaN), const-fold, `Interop.FloatAsInt`, and `AcceleratorRequirements.RequiresFloat4E2M1` (always-true no-op filter like bf16/FP8). The float↔FP4 conversion is **portable bit-manipulation** on every backend (no native cvt → works on every CUDA arch incl. pre-Ampere 1080/2060), byte-identical across all 6.
+- **Fixed a real latent low-precision store bug (Rule 2a).** On PTX the "low-precision value stored to a wider buffer" guard (`floatBuf[i] = (float)lowpBuf[i]`) covered only bf16, so an FP8 **or** FP4 decode-to-float emitted `st.b8` into the 4-byte slot → read back ~0. Found via the FP4 decode kernel + a PTX dump; generalized the guard to bf16 + Float8E4M3 + Float8E5M2 + Float4E2M1. FP8 decode-to-float was silently broken (untested) before this.
+- **Fixed FP8/FP4 by-value sub-word SCALAR params on Wasm + WebGL.** A by-value 1-byte float scalar (e.g. `scale`/`bias` in a generic relu kernel) fell through the host scalar-marshaling switch (no FP8/FP4 case) → struct-serialized (Wasm: garbage) / uniform never sent (WebGL: arrived as 0). Added FP8 + FP4 to the host widen-to-f32 path next to Half/bf16 (the f32-register model). This was a latent FP8 gap too - FP8 only had buffer round-trip tests, never a scalar-param test.
+- Gates: PMT `Float4E2M1` (round-trip + generic relu with FP4 scalar params + float→FP4 RNE/saturate/NaN) **23/0 all 6 backends**; `GenericPrecision` (Half/bf16/FP4 scalar relu) 30/0; `AcceleratorRequirements` 19/0/1; no regression (`PrecisionConvert_Float8` 16/0, desktop `fp8-verify` 257/257, `bf16-f16-oracle` 65536/65536). New harness `DemoConsole -- fp4-verify` (CPU/OpenCL/CUDA bit-exact: convert 24/24, decode 16/16, relu 256/256). Radix-sort keys for `Float4E2M1` follow in a later release.
+
 ## 4.14.0-local.4 (2026-06-17) - Low-precision data-type parity to 100% (selectable saturating cast + complete radix grid; fixes a WebGL FP8-struct-field bug)
 
 Closes the last parity gaps across the four low-precision float types (`Half`, `BFloat16`, `Float8E4M3`, `Float8E5M2`) so data-type support is feature-complete with no lingering items. Forks bump to `2.0.31`.

ILGPU.Algorithms/ILGPU.Algorithms.csproj

@@ -12,7 +12,7 @@
          SpawnDev.ILGPU.Fork* PackageReference Versions inside SpawnDev.ILGPU.csproj.
          Run `_check-fork-version-sync.bat` at repo root. See the banner comment in
          SpawnDev.ILGPU.csproj for the full procedure. -->
-    <Version>2.0.31</Version>
+    <Version>2.0.32</Version>
     <IsPackable>true</IsPackable>
     <GeneratePackageOnBuild>true</GeneratePackageOnBuild>
   </PropertyGroup>

ILGPU/ILGPU.csproj

@@ -16,7 +16,7 @@
          check on push. Skipping (b) means consumers ship rc.N still pulling old Fork
          transitively and the fix is invisible. See the banner comment in
          SpawnDev.ILGPU.csproj for the full procedure. -->
-    <Version>2.0.31</Version>
+    <Version>2.0.32</Version>
     <IsPackable>true</IsPackable>
     <GeneratePackageOnBuild>true</GeneratePackageOnBuild>
   </PropertyGroup>

SpawnDev.ILGPU.Demo.Shared/UnitTests/BackendTestBase.GenericPrecision.cs

@@ -84,6 +84,14 @@ private async Task RunFP8RoundTrip<T>(Func<float, T> toT, Func<T, float> toF)
             => await RunTest(async accelerator =>
                 await RunPrecisionRoundTripCore<T>(accelerator, toT, toF));
 
+        // FP4 (Float4E2M1) round-trip on all 6 backends (1-byte storage, value in the low nibble,
+        // f32-register compute, portable conversion incl. CUDA). Bit-exact vs the concrete (T)(float)x.
+        [TestMethod]
+        public async Task PrecisionConvert_Float4E2M1_RoundTripBitExact() =>
+            await RunTest(async accelerator =>
+                await RunPrecisionRoundTripCore<global::ILGPU.Float4E2M1>(accelerator,
+                    v => (global::ILGPU.Float4E2M1)v, v => (float)v));
+
         private async Task RunPrecisionRoundTrip<T>(Func<float, T> toT, Func<T, float> toF)
             where T : unmanaged, INumber<T>
             => await RunTest(async accelerator =>
@@ -409,5 +417,94 @@ public async Task Float8E4M3_FromSingleFn_OverflowToNaN() => await RunTest(async
                         $"want 0x{expSat[i]:X2} (saturating: finite overflow -> +-448, +-Inf -> NaN).");
             }
         });
+
+        // FP4 (Float4E2M1) generic INumber relu kernel on all 6 backends - load/store, in-kernel
+        // arithmetic, FP4 const, compare+select, AND by-value FP4 sub-word scalar params (scale/bias).
+        // scale=1.5 / bias=0.5 are EXACTLY representable in E2M1 (so the FP4-rounded scalar params match
+        // their float values); the reference rounds per the f32-register model (round once at the end).
+        // E2M1 has 1 mantissa bit so per-op (CPU) vs round-once (GPU) differ by <=1 step - 0.55 rel tol.
+        [TestMethod]
+        public async Task GenericPrecision_Float4E2M1_RunsAndMatchesCpu() => await RunTest(async accelerator =>
+        {
+            const int n = 256;
+            var st = (global::ILGPU.Float4E2M1)1.5f;
+            var bt = (global::ILGPU.Float4E2M1)0.5f;
+            float sf = (float)st, bf = (float)bt;
+            var x = new global::ILGPU.Float4E2M1[n];
+            var expected = new float[n];
+            for (int i = 0; i < n; i++)
+            {
+                // Cover all 16 input codes repeatedly (low nibble), so every representable FP4 input is hit.
+                byte raw = (byte)(i & 0x0F);
+                x[i] = System.Runtime.CompilerServices.Unsafe.As<byte, global::ILGPU.Float4E2M1>(ref raw);
+                float vf = (float)x[i] * sf + bf;
+                expected[i] = vf > 0f ? vf : 0f;
+            }
+
+            using var inBuf = accelerator.Allocate1D(x);
+            using var outBuf = accelerator.Allocate1D<global::ILGPU.Float4E2M1>(n);
+            var k = accelerator.LoadAutoGroupedStreamKernel<Index1D,
+                ArrayView1D<global::ILGPU.Float4E2M1, Stride1D.Dense>,
+                ArrayView1D<global::ILGPU.Float4E2M1, Stride1D.Dense>,
+                global::ILGPU.Float4E2M1, global::ILGPU.Float4E2M1>(FusedReluGeneric<global::ILGPU.Float4E2M1>);
+            k(n, inBuf.View, outBuf.View, st, bt);
+            await accelerator.SynchronizeAsync();
+            var got = await outBuf.CopyToHostAsync<global::ILGPU.Float4E2M1>();
+
+            for (int i = 0; i < n; i++)
+            {
+                float g = (float)got[i];
+                float tol = MathF.Max(MathF.Abs(expected[i]), 1f) * 0.55f;
+                if (MathF.Abs(g - expected[i]) > tol)
+                    throw new Exception(
+                        $"Generic Float4E2M1 kernel @{i} ({BackendName}): in {(float)x[i]} -> got {g}, want " +
+                        $"{expected[i]} (tol {tol}) - FP4 by-value sub-word scalar params + arith must transpile.");
+            }
+        });
+
+        // FP4 (Float4E2M1) float->FP4 convert (E2M1FN, the NVFP4/MXFP4 element format): RNE among the 16
+        // codes; finite overflow AND +-Inf saturate to +-6 (0x7/0xF); NaN -> -0 (0x8). Bit-exact vs the
+        // managed conversion (CPU-verified bit-exact to ml_dtypes.float4_e2m1fn). Proves every backend's
+        // f32->FP4 emitter matches - the overflow-saturate + NaN->-0 branches are the point.
+        private static void Float4ConvertKernel(Index1D i,
+            ArrayView1D<float, Stride1D.Dense> x, ArrayView1D<global::ILGPU.Float4E2M1, Stride1D.Dense> y) =>
+            y[i] = (global::ILGPU.Float4E2M1)x[i];
+
+        [TestMethod]
+        public async Task Float4E2M1_FloatToFP4_RneSaturateNaN() => await RunTest(async accelerator =>
+        {
+            float[] inputs =
+            {
+                0f, 0.5f, 1f, 1.5f, 2f, 3f, 4f, 6f,                       // exact magnitudes
+                0.25f, 0.7f, 1.25f, 2.5f, 5f, 0.75f,                     // RNE (0.25->0, 2.5->2, 5->4 ties-to-even)
+                7f, 100f, 1e30f, float.PositiveInfinity,                  // overflow + +Inf -> +6
+                -0.5f, -1.5f, -6f, -7f, -100f, float.NegativeInfinity,    // negatives + -Inf -> -6
+                float.NaN, -0f,                                           // NaN -> 0x8 (-0); -0 -> 0x8
+            };
+            int n = inputs.Length;
+            var expected = new byte[n];
+            for (int i = 0; i < n; i++)
+            {
+                var v = (global::ILGPU.Float4E2M1)inputs[i];   // managed = oracle-proven reference
+                expected[i] = (byte)(System.Runtime.CompilerServices.Unsafe.As<global::ILGPU.Float4E2M1, byte>(ref v) & 0x0F);
+            }
+
+            using var inBuf = accelerator.Allocate1D(inputs);
+            using var outBuf = accelerator.Allocate1D<global::ILGPU.Float4E2M1>(n);
+            var k = accelerator.LoadAutoGroupedStreamKernel<Index1D,
+                ArrayView1D<float, Stride1D.Dense>, ArrayView1D<global::ILGPU.Float4E2M1, Stride1D.Dense>>(Float4ConvertKernel);
+            k(n, inBuf.View, outBuf.View);
+            await accelerator.SynchronizeAsync();
+            var got = await outBuf.CopyToHostAsync<global::ILGPU.Float4E2M1>();
+
+            for (int i = 0; i < n; i++)
+            {
+                byte g = (byte)(System.Runtime.CompilerServices.Unsafe.As<global::ILGPU.Float4E2M1, byte>(ref got[i]) & 0x0F);
+                if (g != expected[i])
+                    throw new Exception(
+                        $"float->Float4E2M1 kernel @{i} ({BackendName}): input {inputs[i]} -> got 0x{g:X1}, " +
+                        $"want 0x{expected[i]:X1} (E2M1FN: RNE, overflow/+-Inf -> +-6, NaN -> 0x8).");
+            }
+        });
     }
 }

SpawnDev.ILGPU.DemoConsole/AcceleratorRequirementsTests.cs

@@ -59,21 +59,22 @@ public Task Satisfies_Atomics_PassesOnCpu()
     public Task Satisfies_LowPrecisionFloats_AllDevicesPass()
     {
         using var context = Context.CreateDefault();
-        // bf16 + both FP8 formats are supported (always emulated) on every backend, so these are
+        // bf16 + both FP8 formats + FP4 are supported (always emulated) on every backend, so these are
         // no-op documentation filters - every device must satisfy them, including combined.
         var req = new AcceleratorRequirements
         {
             RequiresFloat16 = true,
             RequiresBFloat16 = true,
             RequiresFloat8E4M3 = true,
             RequiresFloat8E5M2 = true,
+            RequiresFloat4E2M1 = true,
         };
         foreach (var device in context.Devices)
         {
             if (!device.Satisfies(req))
                 throw new Exception(
                     $"Device {device.AcceleratorType} (name={device.Name}) failed the low-precision-float " +
-                    $"requirements - Half/bf16/FP8 are supported on every backend and must never filter.");
+                    $"requirements - Half/bf16/FP8/FP4 are supported on every backend and must never filter.");
         }
         return Task.CompletedTask;
     }

SpawnDev.ILGPU/AcceleratorRequirements.cs

@@ -96,6 +96,15 @@ public sealed class AcceleratorRequirements
     /// </summary>
     public bool RequiresFloat8E5M2 { get; init; }
 
+    /// <summary>
+    /// Kernel uses the 4-bit float <c>ILGPU.Float4E2M1</c> (E2M1FN: 1/2/1, bias 1, no Inf/NaN, 16 finite
+    /// codes {0,.5,1,1.5,2,3,4,6}, saturates to +-6 - the NVFP4/MXFP4 element format). Every backend
+    /// supports it - always emulated (1-byte storage with the value in the low nibble, f32-register
+    /// compute, portable conversion on every backend incl. CUDA). Like <see cref="RequiresBFloat16"/>
+    /// this is a no-op documentation filter - it never rules out a backend.
+    /// </summary>
+    public bool RequiresFloat4E2M1 { get; init; }
+
     /// <summary>
     /// Kernel uses Float64 (<c>double</c>). True is compatible with every backend - WebGPU
     /// and WebGL run Float64 through Dekker emulation (see <c>CLAUDE.md</c>). Use
@@ -252,6 +261,7 @@ public static bool Satisfies(this Device device, AcceleratorRequirements require
         if (requirements.RequiresBFloat16 && !HasBFloat16(device)) return false;
         if (requirements.RequiresFloat8E4M3 && !HasFloat8(device)) return false;
         if (requirements.RequiresFloat8E5M2 && !HasFloat8(device)) return false;
+        if (requirements.RequiresFloat4E2M1 && !HasFloat4(device)) return false;
         if (requirements.RequiresFloat64 && !HasFloat64(device)) return false;
         if (requirements.RequiresFloat64Native && !HasFloat64Native(device)) return false;
         if (requirements.RequiresFloat64Strict && !HasFloat64Strict(device)) return false;
@@ -307,6 +317,10 @@ private static bool HasFloat16(Device device)
     // f32-register compute, portable conversion on every backend incl. CUDA). Always true.
     private static bool HasFloat8(Device device) => true;
 
+    // Every backend supports FP4 (Float4E2M1) - always emulated (1-byte storage, value in the low
+    // nibble, f32-register compute, portable conversion on every backend incl. CUDA). Always true.
+    private static bool HasFloat4(Device device) => true;
+
     private static bool HasFloat16Native(Device device)
     {
         // Native-or-nothing: CUDA (SM_53+), OpenCL w/ cl_khr_fp16. WebGPU with shader-f16
@@ -388,6 +402,7 @@ public static string Describe(this AcceleratorRequirements r)
         if (r.RequiresBFloat16) flags.Add("BFloat16");
         if (r.RequiresFloat8E4M3) flags.Add("Float8E4M3");
         if (r.RequiresFloat8E5M2) flags.Add("Float8E5M2");
+        if (r.RequiresFloat4E2M1) flags.Add("Float4E2M1");
         if (r.RequiresFloat64) flags.Add("Float64");
         if (r.RequiresFloat64Native) flags.Add("Float64Native");
         if (r.RequiresFloat64Strict) flags.Add("Float64Strict");

SpawnDev.ILGPU/SpawnDev.ILGPU.csproj

@@ -4,7 +4,7 @@
 		<TargetFramework>net10.0</TargetFramework>
 		<ImplicitUsings>enable</ImplicitUsings>
 		<Nullable>enable</Nullable>
-		<Version>4.14.0-local.4</Version>
+		<Version>4.14.0-local.5</Version>
 		<!-- Brief current-version highlights only. Full per-version history with code samples lives in CHANGELOG.md (linked from the README). -->
 		<PackageReleaseNotes>4.14.0 brings the four low-precision float types (Half, BFloat16, Float8E4M3, Float8E5M2) to feature-complete parity. A selectable saturating cast (FromSingle(x, saturate) / FromSingleSaturating) is available on every type for the NVIDIA-TE/OCP clamp-instead-of-overflow mode, and radix-sort is complete for all four (keys + key/value pairs, ascending + descending) on all 6 backends. It also fixes low-precision CONVERSION CORRECTNESS against the references. (1) Half (float-&gt;half) is now IEEE round-to-nearest-even on every backend (CPU + WebGPU + WebGL + Wasm), bit-exact to numpy.float16 / PyTorch / CUDA / OpenCL - it previously truncated toward zero and flushed subnormals to zero (diverging from numpy AND from CUDA/OpenCL). (2) Float8E4M3 is now bit-exact to PyTorch/JAX/ml_dtypes float8_e4m3fn: the cast + IR convert use the fn convention (finite overflow AND +-Inf -&gt; NaN; was saturate to +-448); saturating is opt-in via Float8E4M3.FromSingleSaturating. BFloat16 was already bit-exact to ml_dtypes.bfloat16 (verified). All validated exhaustively against ml_dtypes/numpy oracles + cross-backend PMT gates. 4.13.2 is a packaging fix over 4.13.1: removes stray Wasm/repro JSON files that the Razor SDK swept into the package, and bundles the precompiled-shaders precompiler tool (tools/) that 4.13.0/4.13.1 were missing. The 4.13.x line brings full low-precision floating-point support across ALL 6 backends (CPU, OpenCL, WebGPU, WebGL, Wasm, CUDA): Half, BFloat16, and FP8 (Float8E4M3 + Float8E5M2) - including FP8 radix-sort keys (4.13.1) - plus generic INumber&lt;T&gt; mixed-precision kernels, PrecisionConvert, and bf16/FP8 portability to pre-Ampere CUDA cards (GTX 1080 / RTX 2060). Full per-version history with code samples: CHANGELOG.md at https://github.com/LostBeard/SpawnDev.ILGPU/blob/master/CHANGELOG.md</PackageReleaseNotes>
 		<GeneratePackageOnBuild>True</GeneratePackageOnBuild>
@@ -65,8 +65,8 @@
 		<ProjectReference Include="..\ILGPU.Algorithms\ILGPU.Algorithms.csproj" />
 	</ItemGroup>
 	<ItemGroup Condition="!Exists('$(MSBuildThisFileDirectory)..\ILGPU\ILGPU.csproj')">
-		<PackageReference Include="SpawnDev.ILGPU.Fork" Version="2.0.31" />
-		<PackageReference Include="SpawnDev.ILGPU.Algorithms.Fork" Version="2.0.31" />
+		<PackageReference Include="SpawnDev.ILGPU.Fork" Version="2.0.32" />
+		<PackageReference Include="SpawnDev.ILGPU.Algorithms.Fork" Version="2.0.32" />
 	</ItemGroup>
 
 	<ItemGroup>

SpawnDev.ILGPU/Wasm/Backend/WasmCodeGenerator.cs

@@ -299,6 +299,7 @@ protected static byte GetWasmTypeFromIR(TypeNode type)
                     BasicValueType.BFloat16 => WasmOpCodes.F32, // bf16 promoted to f32 for compute
                     BasicValueType.Float8E4M3 => WasmOpCodes.F32, // FP8 promoted to f32 for compute
                     BasicValueType.Float8E5M2 => WasmOpCodes.F32,
+                    BasicValueType.Float4E2M1 => WasmOpCodes.F32, // FP4 promoted to f32 for compute
                     BasicValueType.Float32 => WasmOpCodes.F32,
                     BasicValueType.Float64 => WasmOpCodes.F64,
                     _ => WasmOpCodes.I32,
@@ -324,6 +325,7 @@ protected static int GetElementSize(BasicValueType type)
                 BasicValueType.BFloat16 => 2, // bf16: 2-byte storage
                 BasicValueType.Float8E4M3 => 1, // FP8: 1-byte storage
                 BasicValueType.Float8E5M2 => 1,
+                BasicValueType.Float4E2M1 => 1, // FP4: 1-byte storage (4-bit value in low nibble)
                 BasicValueType.Float32 => 4,
                 BasicValueType.Float64 => 8,
                 _ => 4,
@@ -1343,6 +1345,8 @@ public virtual void GenerateCode(PrimitiveValue value)
                         ? (float)value.Float8E4M3Value
                         : value.BasicValueType == BasicValueType.Float8E5M2
                         ? (float)value.Float8E5M2Value
+                        : value.BasicValueType == BasicValueType.Float4E2M1
+                        ? (float)value.Float4E2M1Value
                         : value.Float32Value;
                     WasmModuleBuilder.EmitF32Const(Code, f32Const);
                     break;