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| 1 | +using System; |
| 2 | +using System.Linq; |
| 3 | +using System.Threading.Tasks; |
| 4 | +using ILGPU; |
| 5 | +using ILGPU.Runtime; |
| 6 | + |
| 7 | +/// <summary> |
| 8 | +/// Validates the packed 4-bit QInt4 STORE path on the desktop GPU backends (CUDA/OpenCL): |
| 9 | +/// a kernel writes dst[i] = (QInt4)src[i] into an ArrayView<QInt4> (2 nibbles/byte), then the |
| 10 | +/// raw packed bytes are read back and unpacked to confirm every nibble landed in the right byte and |
| 11 | +/// position. N is large so that for every byte the two adjacent threads write its two nibbles |
| 12 | +/// CONCURRENTLY - a non-atomic byte read-modify-write would race and clobber, so this exercises the |
| 13 | +/// atomic-word-RMW requirement (a small-N test can false-pass a racy store). |
| 14 | +/// |
| 15 | +/// The CPU (IL) backend runs the literal managed indexer, whose ref model cannot write a nibble in |
| 16 | +/// place; packed in-kernel stores must fail loud there rather than silently lose writes, so this |
| 17 | +/// harness asserts CPU THROWS (and treats a throw as the expected, correct behavior). |
| 18 | +/// |
| 19 | +/// Run: dotnet run --project SpawnDev.ILGPU.DemoConsole -c Release -- packed-qint4-store-verify |
| 20 | +/// </summary> |
| 21 | +internal static class PackedQInt4StoreVerify |
| 22 | +{ |
| 23 | + private static void StoreKernel(Index1D i, ArrayView<int> src, ArrayView<QInt4> dst) => |
| 24 | + dst[i] = (QInt4)src[i]; |
| 25 | + |
| 26 | + public static Task<int> Run() |
| 27 | + { |
| 28 | + Console.WriteLine("=== Packed QInt4 nibble STORE verification (CPU/CUDA/OpenCL) ==="); |
| 29 | + |
| 30 | + // Large N to force concurrent adjacent-nibble writes into the same byte (race stress). |
| 31 | + int n = 8192; |
| 32 | + int[] src = new int[n]; |
| 33 | + for (int i = 0; i < n; i++) |
| 34 | + src[i] = (i % 16) - 8; // -8..7, sign-extended round-trip |
| 35 | + byte[] expectedPacked = new byte[(n + 1) / 2]; |
| 36 | + for (int k = 0; k < expectedPacked.Length; k++) |
| 37 | + { |
| 38 | + int lo = src[2 * k] & 0xF; |
| 39 | + int hi = src[2 * k + 1] & 0xF; |
| 40 | + expectedPacked[k] = (byte)(lo | (hi << 4)); |
| 41 | + } |
| 42 | + |
| 43 | + int totalFails = 0; |
| 44 | + using var ctx = Context.Create(b => b.Default().EnableAlgorithms()); |
| 45 | + foreach (var dev in ctx) |
| 46 | + { |
| 47 | + var type = dev.AcceleratorType; |
| 48 | + if (type != AcceleratorType.CPU && type != AcceleratorType.Cuda && type != AcceleratorType.OpenCL) |
| 49 | + continue; |
| 50 | + |
| 51 | + using var acc = dev.CreateAccelerator(ctx); |
| 52 | + |
| 53 | + // CPU (IL) backend: the literal managed ref indexer cannot address a nibble for a write. |
| 54 | + // The correct behavior is a loud failure (UnsupportedKernelFeatureException), not a silent |
| 55 | + // lost write. Accept either a compile/dispatch throw OR a detectable wrong result -> the |
| 56 | + // former is the intended contract. |
| 57 | + if (type == AcceleratorType.CPU) |
| 58 | + { |
| 59 | + bool threw = false; |
| 60 | + try |
| 61 | + { |
| 62 | + using var xBufCpu = acc.Allocate1D<int>(src); |
| 63 | + using var dBufCpu = acc.Allocate1D<QInt4>(n); |
| 64 | + var kCpu = acc.LoadAutoGroupedStreamKernel<Index1D, ArrayView<int>, ArrayView<QInt4>>(StoreKernel); |
| 65 | + kCpu((int)n, xBufCpu.View, dBufCpu.View); |
| 66 | + acc.Synchronize(); |
| 67 | + } |
| 68 | + catch (Exception ex) |
| 69 | + { |
| 70 | + threw = true; |
| 71 | + Console.WriteLine($" [CPU] STORE fail-loud OK ({ex.GetType().Name})"); |
| 72 | + } |
| 73 | + if (!threw) |
| 74 | + { |
| 75 | + Console.WriteLine(" [CPU] STORE did NOT fail loud - packed in-kernel write must throw on CPU FAIL"); |
| 76 | + totalFails++; |
| 77 | + } |
| 78 | + continue; |
| 79 | + } |
| 80 | + |
| 81 | + try |
| 82 | + { |
| 83 | + using var srcBuf = acc.Allocate1D<int>(src); |
| 84 | + using var dstBuf = acc.Allocate1D<QInt4>(n); |
| 85 | + // Pre-zero the packed buffer so a missed write is detectable. |
| 86 | + var rawZero = ((IContiguousArrayView)dstBuf.View.BaseView).AsRawArrayView(); |
| 87 | + rawZero.CopyFromCPU(new byte[rawZero.Length]); |
| 88 | + |
| 89 | + var kernel = acc.LoadAutoGroupedStreamKernel<Index1D, ArrayView<int>, ArrayView<QInt4>>(StoreKernel); |
| 90 | + kernel((int)n, srcBuf.View, dstBuf.View); |
| 91 | + acc.Synchronize(); |
| 92 | + |
| 93 | + var raw = ((IContiguousArrayView)dstBuf.View.BaseView).AsRawArrayView(); |
| 94 | + byte[] got = new byte[raw.Length]; |
| 95 | + raw.CopyToCPU(got); |
| 96 | + int fails = 0; |
| 97 | + for (int k = 0; k < expectedPacked.Length; k++) |
| 98 | + if (got[k] != expectedPacked[k]) fails++; |
| 99 | + if (fails == 0) |
| 100 | + Console.WriteLine($" [{type}] STORE PASS ({expectedPacked.Length}/{expectedPacked.Length} packed bytes correct, N={n})"); |
| 101 | + else |
| 102 | + { |
| 103 | + var firstBad = Enumerable.Range(0, expectedPacked.Length).First(k => got[k] != expectedPacked[k]); |
| 104 | + Console.WriteLine($" [{type}] STORE FAIL ({fails}/{expectedPacked.Length}); first bad byte {firstBad} got=0x{got[firstBad]:X2} want=0x{expectedPacked[firstBad]:X2}"); |
| 105 | + } |
| 106 | + totalFails += fails; |
| 107 | + } |
| 108 | + catch (Exception ex) |
| 109 | + { |
| 110 | + Console.WriteLine($" [{type}] EXCEPTION: {ex.GetType().Name}: {ex.Message.Split('\n')[0]}"); |
| 111 | + totalFails++; |
| 112 | + } |
| 113 | + } |
| 114 | + |
| 115 | + Console.WriteLine(totalFails == 0 |
| 116 | + ? "=== PACKED QInt4 STORE PASS (CUDA + OpenCL atomic-word-RMW; CPU fail-loud) ===" |
| 117 | + : $"=== PACKED QInt4 STORE: {totalFails} problems ==="); |
| 118 | + return Task.FromResult(totalFails == 0 ? 0 : 1); |
| 119 | + } |
| 120 | +} |
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