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| 1 | +/* |
| 2 | +* This file is part of Luma3DS |
| 3 | +* Copyright (C) 2021 Aurora Wright, TuxSH |
| 4 | +* |
| 5 | +* This program is free software: you can redistribute it and/or modify |
| 6 | +* it under the terms of the GNU General Public License as published by |
| 7 | +* the Free Software Foundation, either version 3 of the License, or |
| 8 | +* (at your option) any later version. |
| 9 | +* |
| 10 | +* This program is distributed in the hope that it will be useful, |
| 11 | +* but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | +* GNU General Public License for more details. |
| 14 | +* |
| 15 | +* You should have received a copy of the GNU General Public License |
| 16 | +* along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | +* |
| 18 | +* Additional Terms 7.b and 7.c of GPLv3 apply to this file: |
| 19 | +* * Requiring preservation of specified reasonable legal notices or |
| 20 | +* author attributions in that material or in the Appropriate Legal |
| 21 | +* Notices displayed by works containing it. |
| 22 | +* * Prohibiting misrepresentation of the origin of that material, |
| 23 | +* or requiring that modified versions of such material be marked in |
| 24 | +* reasonable ways as different from the original version. |
| 25 | +*/ |
| 26 | + |
| 27 | +#pragma once |
| 28 | + |
| 29 | +#include "types.h" |
| 30 | + |
| 31 | +typedef struct GpioRegisters { |
| 32 | + u8 gpio1_data; |
| 33 | + u8 _0x001[0x010 - 0x001]; |
| 34 | + |
| 35 | + u8 gpio2_data; |
| 36 | + u8 gpio2_dir; |
| 37 | + u8 gpio2_intcfg; |
| 38 | + u8 gpio2_inten; |
| 39 | + u16 gpio2_data2; |
| 40 | + u8 _0x016[0x020 - 0x016]; |
| 41 | + |
| 42 | + u16 gpio3_data; |
| 43 | + u16 gpio3_dir; |
| 44 | + u16 gpio3_intcfg; |
| 45 | + u16 gpio3_inten; |
| 46 | + u16 gpio3_data2; |
| 47 | + u8 _0x02a[0x100 - 0x02A]; |
| 48 | +} GpioRegisters; |
| 49 | + |
| 50 | +typedef enum GpioDirection { |
| 51 | + GPIO_DIR_INPUT = 0, |
| 52 | + GPIO_DIR_OUTPUT = 1, |
| 53 | +} GpioDirection; |
| 54 | + |
| 55 | +typedef enum GpioInterruptConfig { |
| 56 | + GPIO_INTCFG_FALLING_EDGE = 0, |
| 57 | + GPIO_INTCFG_RISING_EDGE = 1, |
| 58 | +} GpioInterruptConfig; |
| 59 | + |
| 60 | +#define GPIO_PIN(bank, idx) (((bank) << 4) | ((idx) & 0xF)) |
| 61 | +#define BANK_OF(pin) ((pin) >> 4) |
| 62 | +#define BIT_OF(pin) ((pin) & 0xF) |
| 63 | + |
| 64 | +typedef enum GpioPin { |
| 65 | + // GPIO1 |
| 66 | + GPIO_DEBUG_BUTTON = GPIO_PIN(1, 0), // active-low |
| 67 | + GPIO_TOUCH_SCREEN = GPIO_PIN(1, 1), // active-low, 0 when the touch screen is pressed |
| 68 | + GPIO_SHELL_CLOSED = GPIO_PIN(1, 2), |
| 69 | + |
| 70 | + // GPIO2 |
| 71 | + GPIO_HEADPHONES_INSERTED = GPIO_PIN(2, 0), |
| 72 | + GPIO_TWL_DEPOP = GPIO_PIN(2, 1), // active-low |
| 73 | + |
| 74 | + // GPIO2 (DATA2) |
| 75 | + GPIO_WIFI_MODE = GPIO_PIN(4, 0), // 0 is CTR, 1 is MP (DS WiFi) |
| 76 | + |
| 77 | + // GPIO3 |
| 78 | + GPIO_CSTICK_INT = GPIO_PIN(3, 0), |
| 79 | + GPIO_IRDA_INT = GPIO_PIN(3, 1), // active-low |
| 80 | + GPIO_GYRO_INT = GPIO_PIN(3, 2), |
| 81 | + GPIO_CSTICK_STOP = GPIO_PIN(3, 3), // output |
| 82 | + GPIO_IRDA_TXRC = GPIO_PIN(3, 4), // output |
| 83 | + GPIO_IRDA_RXD = GPIO_PIN(3, 5), // active-low |
| 84 | + GPIO_NFC_OUT1 = GPIO_PIN(3, 6), // output |
| 85 | + GPIO_NFC_OUT2 = GPIO_PIN(3, 7), // output |
| 86 | + GPIO_HEADPHONES_BUTTON = GPIO_PIN(3, 8), // active-low ("half-inserted") |
| 87 | + GPIO_MCU_INT = GPIO_PIN(3, 9), |
| 88 | + GPIO_NFC_INT = GPIO_PIN(3, 10), |
| 89 | + GPIO_QTM_OUT = GPIO_PIN(3, 11), // output |
| 90 | + |
| 91 | + // GPIO3 (DATA2) |
| 92 | + GPIO_WIFI_ENABLED = GPIO_PIN(5, 0), |
| 93 | +} GpioPin; |
| 94 | + |
| 95 | +static volatile GpioRegisters *const GPIO = (volatile GpioRegisters *)0x10147000; |
| 96 | + |
| 97 | +static inline bool gpioRead(GpioPin pin) |
| 98 | +{ |
| 99 | + u32 bank = BANK_OF(pin); |
| 100 | + u32 bit = BIT_OF(pin); |
| 101 | + |
| 102 | + switch (bank) { |
| 103 | + case 1: |
| 104 | + return (GPIO->gpio1_data & BIT(bit)) != 0; |
| 105 | + case 2: |
| 106 | + return (GPIO->gpio2_data & BIT(bit)) != 0; |
| 107 | + case 3: |
| 108 | + return (GPIO->gpio3_data & BIT(bit)) != 0; |
| 109 | + case 4: |
| 110 | + return (GPIO->gpio2_data2 & BIT(bit)) != 0; |
| 111 | + case 5: |
| 112 | + return (GPIO->gpio3_data2 & BIT(bit)) != 0; |
| 113 | + |
| 114 | + default: |
| 115 | + return false; |
| 116 | + } |
| 117 | +} |
| 118 | + |
| 119 | +static inline void gpioWrite(GpioPin pin, bool val) |
| 120 | +{ |
| 121 | + u32 bank = BANK_OF(pin); |
| 122 | + u32 bit = BIT_OF(pin); |
| 123 | + |
| 124 | + u32 valMask = (val ? 1 : 0) << bit; |
| 125 | + u32 tmp; |
| 126 | + |
| 127 | + switch (bank) { |
| 128 | + case 1: |
| 129 | + tmp = GPIO->gpio1_data & ~BIT(bit); |
| 130 | + GPIO->gpio1_data = (u8)(tmp | valMask); |
| 131 | + break; |
| 132 | + case 2: |
| 133 | + tmp = GPIO->gpio2_data & ~BIT(bit); |
| 134 | + GPIO->gpio2_data = (u8)(tmp | valMask); |
| 135 | + break; |
| 136 | + case 3: |
| 137 | + tmp = GPIO->gpio3_data & ~BIT(bit); |
| 138 | + GPIO->gpio3_data = (u16)(tmp | valMask); |
| 139 | + break; |
| 140 | + case 4: |
| 141 | + tmp = GPIO->gpio2_data2 & ~BIT(bit); |
| 142 | + GPIO->gpio2_data2 = (u16)(tmp | valMask); |
| 143 | + break; |
| 144 | + case 5: |
| 145 | + tmp = GPIO->gpio3_data2 & ~BIT(bit); |
| 146 | + GPIO->gpio3_data2 = (u16)(tmp | valMask); |
| 147 | + break; |
| 148 | + |
| 149 | + default: |
| 150 | + break; |
| 151 | + } |
| 152 | +} |
| 153 | + |
| 154 | +static inline void gpioSetDirection(GpioPin pin, GpioDirection direction) |
| 155 | +{ |
| 156 | + u32 bank = BANK_OF(pin); |
| 157 | + u32 bit = BIT_OF(pin); |
| 158 | + |
| 159 | + u32 valMask = (direction == GPIO_DIR_OUTPUT ? 1 : 0) << bit; |
| 160 | + u32 tmp; |
| 161 | + |
| 162 | + switch (bank) { |
| 163 | + case 2: |
| 164 | + tmp = GPIO->gpio2_dir & ~BIT(bit); |
| 165 | + GPIO->gpio2_dir = (u8)(tmp | valMask); |
| 166 | + break; |
| 167 | + case 3: |
| 168 | + tmp = GPIO->gpio3_dir & ~BIT(bit); |
| 169 | + GPIO->gpio3_dir = (u16)(tmp | valMask); |
| 170 | + break; |
| 171 | + |
| 172 | + default: |
| 173 | + break; |
| 174 | + } |
| 175 | +} |
| 176 | + |
| 177 | +static inline void gpioConfigureInterrupt(GpioPin pin, GpioInterruptConfig cfg) |
| 178 | +{ |
| 179 | + u32 bank = BANK_OF(pin); |
| 180 | + u32 bit = BIT_OF(pin); |
| 181 | + |
| 182 | + u32 valMask = (cfg == GPIO_INTCFG_RISING_EDGE ? 1 : 0) << bit; |
| 183 | + u32 tmp; |
| 184 | + |
| 185 | + switch (bank) { |
| 186 | + case 2: |
| 187 | + tmp = GPIO->gpio2_intcfg & ~BIT(bit); |
| 188 | + GPIO->gpio2_intcfg = (u8)(tmp | valMask); |
| 189 | + break; |
| 190 | + case 3: |
| 191 | + tmp = GPIO->gpio3_data & ~BIT(bit); |
| 192 | + GPIO->gpio3_intcfg = (u16)(tmp | valMask); |
| 193 | + break; |
| 194 | + |
| 195 | + default: |
| 196 | + break; |
| 197 | + } |
| 198 | +} |
| 199 | + |
| 200 | +static inline void gpioSetInterruptEnabled(GpioPin pin, bool enabled) |
| 201 | +{ |
| 202 | + u32 bank = BANK_OF(pin); |
| 203 | + u32 bit = BIT_OF(pin); |
| 204 | + |
| 205 | + u32 valMask = (enabled ? 1 : 0) << bit; |
| 206 | + u32 tmp; |
| 207 | + |
| 208 | + switch (bank) { |
| 209 | + case 2: |
| 210 | + tmp = GPIO->gpio2_inten & ~BIT(bit); |
| 211 | + GPIO->gpio2_inten = (u8)(tmp | valMask); |
| 212 | + break; |
| 213 | + case 3: |
| 214 | + tmp = GPIO->gpio3_inten & ~BIT(bit); |
| 215 | + GPIO->gpio3_inten = (u16)(tmp | valMask); |
| 216 | + break; |
| 217 | + |
| 218 | + default: |
| 219 | + break; |
| 220 | + } |
| 221 | +} |
| 222 | + |
| 223 | +#undef GPIO_PIN |
| 224 | +#undef BIT_OF |
| 225 | +#undef BANK_OF |
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