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outercloudstudiooutercloudstudio
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fix reading correct color
1 parent ebe353d commit 0573e31

3 files changed

Lines changed: 16 additions & 25 deletions

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‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -61,9 +61,7 @@ module Top(
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.io_hsync (vgaHSync),
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.io_vsync (vgaVSync),
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.io_rgb (rgb),
64-
.io_blanking (blanking),
65-
.io_hPos (),
66-
.io_vPos ()
64+
.io_blanking (blanking)
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);
6866

6967
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr‎

Lines changed: 12 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -90,79 +90,72 @@
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<FileSets Version="1" Minor="32">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
93-
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
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<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
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<File Path="$PSRCDIR/sources_1/new/VGATop.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/Decoder.sv">
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<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/Main.sv">
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<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
125-
<File Path="$PPRDIR/../generated/Memory.sv">
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<File Path="$PPRDIR/../generated/Decoder.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/Registers.sv">
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<File Path="$PPRDIR/../generated/Main.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/memory_1024x32.sv">
137+
<File Path="$PPRDIR/../generated/Memory.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
149-
<File Path="$PSRCDIR/sources_1/new/top.v">
144+
<File Path="$PPRDIR/../generated/Registers.sv">
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<FileInfo>
151-
<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
157-
<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
151+
<File Path="$PPRDIR/../generated/VGAController.sv">
158152
<FileInfo>
159-
<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
165-
<File Path="$PPRDIR/../generated/VGAController.sv">
158+
<File Path="$PPRDIR/../generated/memory_1024x32.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
@@ -176,7 +169,7 @@
176169
<Attr Name="UsedIn" Val="simulation"/>
177170
</FileInfo>
178171
</File>
179-
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
172+
<File Path="$PSRCDIR/sources_1/new/top.v">
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<FileInfo>
181174
<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
@@ -185,7 +178,7 @@
185178
</File>
186179
<Config>
187180
<Option Name="DesignMode" Val="RTL"/>
188-
<Option Name="TopModule" Val="VGATop"/>
181+
<Option Name="TopModule" Val="Top"/>
189182
</Config>
190183
</FileSet>
191184
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">

‎src/main/scala/RISCV/VGAController.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ class VGAController extends Module {
2020
val io = IO(new Bundle {
2121
val address = Input(UInt(32.W))
2222
val write = Input(Bool())
23-
val write_value = Input(UInt(32.W))
23+
val write_value = Input(UInt(8.W))
2424

2525
val hsync = Output(Bool())
2626
val vsync = Output(Bool())
@@ -66,9 +66,9 @@ class VGAController extends Module {
6666
val read_address = WireInit(0.U(32.W))
6767

6868
when(active) {
69-
read_address := 0.U
69+
read_address := vCount / 2.U * 320.U + hCount / 2.U + 1.U
7070
}.otherwise {
71-
read_address := vCount * 320.U + hCount
71+
read_address := (vCount + 1.U) / 2.U * 320.U
7272
}
7373

7474
val color = memory.read(read_address, true.B)

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