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outercloudstudiooutercloudstudio
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cleanup some claude stuff
1 parent 36235b1 commit 10a0d84

1 file changed

Lines changed: 50 additions & 96 deletions

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‎src/main/scala/RISCV/Main.scala‎

Lines changed: 50 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ class Main() extends Module {
5656
val decoder = Module(new Decoder())
5757
decoder.io.instruction := 0.U;
5858

59-
// 0 - Fetch 1 - Latch fetch 2 - Decode/Execute 3 - Wait for load/store mem 4 - Complete load/store
59+
// 0 - Load Instruction 1 - Execute Instruction A 2 - Execute Instruction B
6060
val stage = RegInit(0.U(3.W));
6161

6262
memory.io.write_1 := false.B
@@ -81,29 +81,15 @@ class Main() extends Module {
8181
val rs2_buffer = RegInit(0.U(5.W));
8282
val rd_buffer = RegInit(0.U(5.W));
8383

84-
val data_buffer_1 = RegInit(0.U(32.W));
85-
val data_buffer_2 = RegInit(0.U(32.W));
86-
87-
val isLoadStore = decoder.io.operation === "b000_0000011".U || // LB
88-
decoder.io.operation === "b001_0000011".U || // LH
89-
decoder.io.operation === "b010_0000011".U || // LW
90-
decoder.io.operation === "b100_0000011".U || // LBU
91-
decoder.io.operation === "b101_0000011".U || // LHU
92-
decoder.io.operation === "b000_0100011".U || // SB
93-
decoder.io.operation === "b001_0100011".U || // SH
94-
decoder.io.operation === "b010_0100011".U // SW
95-
96-
97-
9884
when(io.execute) {
9985
printf("\n");
10086
printf("Stage: %d\n", stage);
10187

102-
when(stage =/= 0.U && stage =/= 1.U && stage =/= 3.U) {
88+
when(stage =/= 0.U) {
10389
printf("Operation: %b\n", decoder.io.operation);
10490
printf("Program Pointer: %d\n", program_pointer);
105-
printf("Data 1: %b\n", data_buffer_1);
106-
printf("Data 2: %b\n", data_buffer_2);
91+
printf("Data 1: %b\n", memory.io.read_value_1);
92+
printf("Data 2: %b\n", memory.io.read_value_2);
10793
printf("Register 1: %b\n", registers.io.debug_1);
10894
printf("Register 2: %b\n", registers.io.debug_2);
10995
printf("Register 3: %b\n", registers.io.debug_3);
@@ -116,28 +102,21 @@ class Main() extends Module {
116102
printf("Register10: %b\n", registers.io.debug_10);
117103
}
118104

119-
// Stage 0: Present address to memory for instruction fetch
105+
stage := stage + 1.U;
106+
120107
when(stage === 0.U) {
121108
memory.io.read_1 := true.B
122109
memory.io.address_1 := program_pointer / 4.U
123-
stage := 1.U
124110
}
125111

126-
// Stage 1: Latch memory output into registers (SyncReadMem data available now)
127112
when(stage === 1.U) {
128-
data_buffer_1 := memory.io.read_value_1
129-
data_buffer_2 := memory.io.read_value_2
130-
stage := 2.U
131-
}
113+
decoder.io.instruction := memory.io.read_value_1
132114

133-
// Stage 2: Data is now in data_buffer_1, decode and execute
134-
when(stage === 2.U) {
135-
decoder.io.instruction := data_buffer_1
136-
operation_buffer := decoder.io.operation;
137-
immediate_buffer := decoder.io.immediate;
138-
rs1_buffer := decoder.io.rs1;
139-
rs2_buffer := decoder.io.rs2;
140-
rd_buffer := decoder.io.rd;
115+
operation_buffer := decoder.io.operation
116+
immediate_buffer := decoder.io.immediate
117+
rs1_buffer := decoder.io.rs1
118+
rs2_buffer := decoder.io.rs2
119+
rd_buffer := decoder.io.rd
141120

142121
switch(decoder.io.operation) {
143122
// LB
@@ -149,8 +128,6 @@ class Main() extends Module {
149128
memory.io.read_2 := true.B
150129
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
151130

152-
stage := 3.U
153-
154131
printf(
155132
"[LB] Rs1: %d Immediate: %b\n",
156133
decoder.io.rs1,
@@ -167,8 +144,6 @@ class Main() extends Module {
167144
memory.io.read_2 := true.B
168145
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
169146

170-
stage := 3.U
171-
172147
printf(
173148
"[LH] Rs1: %d Immediate: %b\n",
174149
decoder.io.rs1,
@@ -185,8 +160,6 @@ class Main() extends Module {
185160
memory.io.read_2 := true.B
186161
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
187162

188-
stage := 3.U
189-
190163
printf(
191164
"[LW] Rs1: %d Immediate: %b\n",
192165
decoder.io.rs1,
@@ -203,8 +176,6 @@ class Main() extends Module {
203176
memory.io.read_2 := true.B
204177
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
205178

206-
stage := 3.U
207-
208179
printf(
209180
"[LBU] Rs1: %d Immediate: %b\n",
210181
decoder.io.rs1,
@@ -221,8 +192,6 @@ class Main() extends Module {
221192
memory.io.read_2 := true.B
222193
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
223194

224-
stage := 3.U
225-
226195
printf(
227196
"[LHU] Rs1: %d Immediate: %b\n",
228197
decoder.io.rs1,
@@ -238,8 +207,6 @@ class Main() extends Module {
238207
memory.io.read_1 := true.B
239208
memory.io.address_1 := (registers.io.out_a + decoder.io.immediate) / 4.U;
240209

241-
stage := 3.U
242-
243210
printf(
244211
"[SB] Rs1: %d Rs2: %d Immediate: %b\n",
245212
decoder.io.rs1,
@@ -258,8 +225,6 @@ class Main() extends Module {
258225
memory.io.read_2 := true.B
259226
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
260227

261-
stage := 3.U
262-
263228
printf(
264229
"[SH] Rs1: %d Rs2: %d Immediate: %b\n",
265230
decoder.io.rs1,
@@ -277,9 +242,7 @@ class Main() extends Module {
277242
memory.io.address_1 := (registers.io.out_a + decoder.io.immediate) / 4.U;
278243
memory.io.read_2 := true.B
279244
memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
280-
281-
stage := 3.U
282-
245+
283246
printf(
284247
"[SW] Rs1: %d Rs2: %d Immediate: %b Raw Address: %b\n",
285248
decoder.io.rs1,
@@ -888,14 +851,7 @@ class Main() extends Module {
888851
}
889852
}
890853

891-
// Stage 3: Latch load/store memory results
892-
when(stage === 3.U) {
893-
data_buffer_1 := memory.io.read_value_1
894-
data_buffer_2 := memory.io.read_value_2
895-
stage := 4.U
896-
}
897-
898-
when(stage === 4.U) {
854+
when(stage === 2.U) {
899855
stage := 0.U;
900856

901857
switch(operation_buffer) {
@@ -906,7 +862,7 @@ class Main() extends Module {
906862

907863
val address = registers.io.out_a + immediate_buffer
908864
val data =
909-
(data_buffer_1 >> (address % 4.U) * 8.U) | (data_buffer_2 << (4.U - (address % 4.U)) * 8.U)
865+
(memory.io.read_value_1 >> (address % 4.U) * 8.U) | (memory.io.read_value_2 << (4.U - (address % 4.U)) * 8.U)
910866

911867
registers.io.in := Fill(24, data(7)) ## data(7, 0)
912868

@@ -926,7 +882,7 @@ class Main() extends Module {
926882

927883
val address = registers.io.out_a + immediate_buffer
928884
val data =
929-
(data_buffer_1 >> (address % 4.U) * 8.U) | (data_buffer_2 << (4.U - (address % 4.U)) * 8.U)
885+
(memory.io.read_value_1 >> (address % 4.U) * 8.U) | (memory.io.read_value_2 << (4.U - (address % 4.U)) * 8.U)
930886

931887
registers.io.in := Fill(16, data(15)) ## data(15, 0)
932888

@@ -946,7 +902,7 @@ class Main() extends Module {
946902

947903
val address = registers.io.out_a + immediate_buffer
948904
val data =
949-
(data_buffer_1 >> (address % 4.U) * 8.U) | (data_buffer_2 << (4.U - (address % 4.U)) * 8.U)
905+
(memory.io.read_value_1 >> (address % 4.U) * 8.U) | (memory.io.read_value_2 << (4.U - (address % 4.U)) * 8.U)
950906

951907
registers.io.in := data
952908

@@ -966,7 +922,7 @@ class Main() extends Module {
966922

967923
val address = registers.io.out_a + immediate_buffer
968924
val data =
969-
(data_buffer_1 >> (address % 4.U) * 8.U) | (data_buffer_2 << (4.U - (address % 4.U)) * 8.U)
925+
(memory.io.read_value_1 >> (address % 4.U) * 8.U) | (memory.io.read_value_2 << (4.U - (address % 4.U)) * 8.U)
970926

971927
registers.io.in := 0.U(24.W) ## data(7, 0)
972928

@@ -986,7 +942,7 @@ class Main() extends Module {
986942

987943
val address = registers.io.out_a + immediate_buffer
988944
val data =
989-
(data_buffer_1 >> (address % 4.U) * 8.U) | (data_buffer_2 << (4.U - (address % 4.U)) * 8.U)
945+
(memory.io.read_value_1 >> (address % 4.U) * 8.U) | (memory.io.read_value_2 << (4.U - (address % 4.U)) * 8.U)
990946

991947
registers.io.in := 0.U(16.W) ## data(15, 0)
992948

@@ -1007,33 +963,33 @@ class Main() extends Module {
1007963
val address = registers.io.out_a + immediate_buffer
1008964

1009965
val value_1 =
1010-
WireDefault(data_buffer_1)
966+
WireDefault(memory.io.read_value_1)
1011967

1012968
switch(address % 4.U) {
1013969
is(0.U) {
1014970
value_1 := Cat(
1015-
data_buffer_1(31, 8),
971+
memory.io.read_value_1(31, 8),
1016972
registers.io.out_b(7, 0)
1017973
)
1018974
}
1019975
is(1.U) {
1020976
value_1 := Cat(
1021-
data_buffer_1(31, 16),
977+
memory.io.read_value_1(31, 16),
1022978
registers.io.out_b(7, 0),
1023-
data_buffer_1(7, 0)
979+
memory.io.read_value_1(7, 0)
1024980
)
1025981
}
1026982
is(2.U) {
1027983
value_1 := Cat(
1028-
data_buffer_1(31, 24),
984+
memory.io.read_value_1(31, 24),
1029985
registers.io.out_b(7, 0),
1030-
data_buffer_1(15, 0)
986+
memory.io.read_value_1(15, 0)
1031987
)
1032988
}
1033989
is(3.U) {
1034990
value_1 := Cat(
1035991
registers.io.out_b(7, 0),
1036-
data_buffer_1(23, 0)
992+
memory.io.read_value_1(23, 0)
1037993
)
1038994
}
1039995
}
@@ -1054,39 +1010,39 @@ class Main() extends Module {
10541010

10551011
val address = registers.io.out_a + immediate_buffer
10561012

1057-
val value_1 = WireDefault(data_buffer_1)
1058-
val value_2 = WireDefault(data_buffer_2)
1013+
val value_1 = WireDefault(memory.io.read_value_1)
1014+
val value_2 = WireDefault(memory.io.read_value_2)
10591015

10601016
switch(address % 4.U) {
10611017
is(0.U) {
10621018
value_1 := Cat(
1063-
data_buffer_1(31, 16),
1019+
memory.io.read_value_1(31, 16),
10641020
registers.io.out_b(15, 0)
10651021
)
10661022
}
10671023

10681024
is(1.U) {
10691025
value_1 := Cat(
1070-
data_buffer_1(31, 24),
1026+
memory.io.read_value_1(31, 24),
10711027
registers.io.out_b(15, 0),
1072-
data_buffer_1(7, 0)
1028+
memory.io.read_value_1(7, 0)
10731029
)
10741030
}
10751031

10761032
is(2.U) {
10771033
value_1 := Cat(
10781034
registers.io.out_b(15, 0),
1079-
data_buffer_1(15, 0)
1035+
memory.io.read_value_1(15, 0)
10801036
)
10811037
}
10821038

10831039
is(3.U) {
10841040
value_1 := Cat(
10851041
registers.io.out_b(7, 0),
1086-
data_buffer_1(23, 0)
1042+
memory.io.read_value_1(23, 0)
10871043
)
10881044
value_2 := Cat(
1089-
data_buffer_2(31, 8),
1045+
memory.io.read_value_2(31, 8),
10901046
registers.io.out_b(15, 8)
10911047
)
10921048
}
@@ -1096,11 +1052,10 @@ class Main() extends Module {
10961052
memory.io.address_1 := address / 4.U
10971053
memory.io.write_value_1 := value_1
10981054

1099-
when(address % 4.U === 3.U) {
1100-
memory.io.write_2 := true.B
1101-
memory.io.address_2 := address / 4.U + 1.U
1102-
memory.io.write_value_2 := value_2
1103-
}
1055+
memory.io.write_2 := true.B
1056+
memory.io.address_2 := address / 4.U + 1.U
1057+
memory.io.write_value_2 := value_2
1058+
11041059
program_pointer := program_pointer + 4.U
11051060

11061061
printf("[SH]\n")
@@ -1113,8 +1068,8 @@ class Main() extends Module {
11131068

11141069
val address = registers.io.out_a + immediate_buffer
11151070

1116-
val value_1 = WireDefault(data_buffer_1)
1117-
val value_2 = WireDefault(data_buffer_2)
1071+
val value_1 = WireDefault(memory.io.read_value_1)
1072+
val value_2 = WireDefault(memory.io.read_value_2)
11181073

11191074
switch(address % 4.U) {
11201075
is(0.U) {
@@ -1124,32 +1079,32 @@ class Main() extends Module {
11241079
is(1.U) {
11251080
value_1 := Cat(
11261081
registers.io.out_b(23, 0),
1127-
data_buffer_1(7, 0)
1082+
memory.io.read_value_1(7, 0)
11281083
)
11291084
value_2 := Cat(
1130-
data_buffer_2(31, 8),
1085+
memory.io.read_value_2(31, 8),
11311086
registers.io.out_b(31, 24)
11321087
)
11331088
}
11341089

11351090
is(2.U) {
11361091
value_1 := Cat(
11371092
registers.io.out_b(15, 0),
1138-
data_buffer_1(15, 0)
1093+
memory.io.read_value_1(15, 0)
11391094
)
11401095
value_2 := Cat(
1141-
data_buffer_2(31, 16),
1096+
memory.io.read_value_2(31, 16),
11421097
registers.io.out_b(31, 16)
11431098
)
11441099
}
11451100

11461101
is(3.U) {
11471102
value_1 := Cat(
11481103
registers.io.out_b(7, 0),
1149-
data_buffer_1(23, 0)
1104+
memory.io.read_value_1(23, 0)
11501105
)
11511106
value_2 := Cat(
1152-
data_buffer_2(31, 24),
1107+
memory.io.read_value_2(31, 24),
11531108
registers.io.out_b(31, 8)
11541109
)
11551110
}
@@ -1159,11 +1114,10 @@ class Main() extends Module {
11591114
memory.io.address_1 := address / 4.U
11601115
memory.io.write_value_1 := value_1
11611116

1162-
when(address % 4.U =/= 0.U) {
1163-
memory.io.write_2 := true.B
1164-
memory.io.address_2 := address / 4.U + 1.U
1165-
memory.io.write_value_2 := value_2
1166-
}
1117+
memory.io.write_2 := true.B
1118+
memory.io.address_2 := address / 4.U + 1.U
1119+
memory.io.write_value_2 := value_2
1120+
11671121
program_pointer := program_pointer + 4.U
11681122

11691123
printf("[SW]\n")

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