Add tasks and move over verilog generation

Author: outercloudstudio

.vscode/tasks.json

@@ -0,0 +1,16 @@
+{
+    "version": "2.0.0",
+    "tasks": [
+        {
+            "label": "Test",
+            "command": "sbt run test",
+            "type": "shell",
+            "args": [],
+            "problemMatcher": [],
+            "presentation": {
+                "reveal": "always"
+            },
+            "group": "build"
+        }
+    ]
+}

src/main/scala/RISCV/EmitVerilog.scala

@@ -0,0 +1,21 @@
+package RISCV
+
+import chisel3._
+import _root_.circt.stage.ChiselStage
+import scala.math._
+
+/**
+  * Object to generate Verilog/SystemVerilog for the module.
+  * Customize firtoolOpts if needed.
+  */
+
+object EmitVerilog extends App {
+//   ChiselStage.emitSystemVerilogFile(
+//     new Registers(),
+//     firtoolOpts = Array(
+//       "-disable-all-randomization",
+//       "-strip-debug-info",
+//       "-default-layer-specialization=enable"
+//     )
+//   )
+}

src/main/scala/RISCV/Hart.scala

@@ -9,6 +9,7 @@ import scala.math._
   *
   * @param width Bit width (default: 32 bits)
   */
+  
 class Hart(val width: Int = 32) extends Module {
     val io = IO(new Bundle {})
 

src/main/scala/RISCV/Registers.scala

@@ -34,18 +34,3 @@ class Registers(val width: Int = 32, val nreg: Int = 5) extends Module {
         regs(io.select) := io.in
     }
 }
-
-/**
-  * Object to generate Verilog/SystemVerilog for the module.
-  * Customize firtoolOpts if needed.
-  */
-object Registers extends App {
-  ChiselStage.emitSystemVerilogFile(
-    new Registers(),
-    firtoolOpts = Array(
-      "-disable-all-randomization",
-      "-strip-debug-info",
-      "-default-layer-specialization=enable"
-    )
-  )
-}