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1 parent 3a1bdc9 commit 3717991Copy full SHA for 3717991
1 file changed
src/main/scala/RISCV/Memory.scala
@@ -37,15 +37,15 @@ class Memory() extends Module {
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io.write_vga := isVGA && io.write_1
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io.write_value_vga := io.write_value_1
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- when(isVGA) {
+ when(io.write_value_1 && isVGA) {
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printf(
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"Writing to VGA! Address: %b Data: %b\n",
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io.address_1 - 0b1000000000000.U,
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io.write_value_1
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);
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}.otherwise {
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- "Writing to VGA! Memory: %b Data: %b\n",
+ "Writing to Memory! Address: %b Data: %b\n",
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