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1 parent 8832345 commit 40c424dCopy full SHA for 40c424d
1 file changed
src/main/scala/RISCV/Memory.scala
@@ -49,13 +49,13 @@ class Memory() extends Module {
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io.address_1,
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io.write_value_1,
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(io.read_1 || io.write_1) && !isVGA,
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- io.write_1 && !isVGA
+ io.write_1
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)
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io.read_value_2 := memory.readWrite(
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io.address_2,
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io.write_value_2,
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- (io.read_2 || io.write_2),
+ (io.read_2 || io.write_2) && !isVGA,
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io.write_2
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