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fix
1 parent c59ae16 commit 6a54e14

2 files changed

Lines changed: 2 additions & 2 deletions

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src/main/scala/RISCV/Memory.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ class Memory() extends Module {
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}.otherwise {
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printf(
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"Writing to Memory! Address: %b Data: %b\n",
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io.address_1 - 0b1000000000000.U,
50+
io.address_1,
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io.write_value_1
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);
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}

src/test/scala/RISCV/MainSpec.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
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dut.clock.step(1)
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dut.io.debug_write_address.poke(3.U)
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dut.io.debug_write_data.poke(0x00008023.U)
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dut.io.debug_write_data.poke(0x00208023.U)
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dut.clock.step(1)
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6262
dut.io.debug_write_address.poke(4.U)

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