@@ -21,58 +21,67 @@ class VGAController extends Module {
2121 val address = Input (UInt (32 .W ))
2222 val write = Input (Bool ())
2323 val write_value = Input (UInt (8 .W ))
24+ val read_clk = Input (Clock ())
2425
2526 val hsync = Output (Bool ())
2627 val vsync = Output (Bool ())
2728 val rgb = Output (UInt (12 .W ))
2829 val blanking = Output (Bool ())
30+
2931 })
3032
3133 val memory = SyncReadMem (320 * 240 , UInt (8 .W ))
3234
33- val hCount = RegInit (0 .U (10 .W ))
34- val vCount = RegInit (0 .U (10 .W ))
35+
3536
3637 when(io.write) {
3738 memory.write(io.address, io.write_value)
3839 }
3940
40- when(hCount === (H_TOTAL - 1 ).U ) {
41- hCount := 0 .U
41+ withClock(io.read_clk) {
42+ val hCount = RegInit (0 .U (10 .W ))
43+ val vCount = RegInit (0 .U (10 .W ))
44+
4245
43- when(vCount === (V_TOTAL - 1 ).U ) {
44- vCount := 0 .U
46+ when(hCount === (H_TOTAL - 1 ).U ) {
47+ hCount := 0 .U
48+
49+ when(vCount === (V_TOTAL - 1 ).U ) {
50+ vCount := 0 .U
51+ }.otherwise {
52+ vCount := vCount + 1 .U
53+ }
4554 }.otherwise {
46- vCount := vCount + 1 .U
55+ hCount := hCount + 1 .U
4756 }
48- }.otherwise {
49- hCount := hCount + 1 .U
50- }
5157
52- val hSyncStart = (H_VISIBLE + H_FRONT ).U
53- val hSyncEnd = (H_VISIBLE + H_FRONT + H_SYNC ).U
54- val vSyncStart = (V_VISIBLE + V_FRONT ).U
55- val vSyncEnd = (V_VISIBLE + V_FRONT + V_SYNC ).U
58+ val hSyncStart = (H_VISIBLE + H_FRONT ).U
59+ val hSyncEnd = (H_VISIBLE + H_FRONT + H_SYNC ).U
60+ val vSyncStart = (V_VISIBLE + V_FRONT ).U
61+ val vSyncEnd = (V_VISIBLE + V_FRONT + V_SYNC ).U
5662
57- io.hsync := ! (hCount >= hSyncStart && hCount < hSyncEnd)
58- io.vsync := ! (vCount >= vSyncStart && vCount < vSyncEnd)
63+ io.hsync := ! (hCount >= hSyncStart && hCount < hSyncEnd)
64+ io.vsync := ! (vCount >= vSyncStart && vCount < vSyncEnd)
5965
60- val hActive = hCount < H_VISIBLE .U
61- val vActive = vCount < V_VISIBLE .U
62- val active = hActive && vActive
66+ val hActive = hCount < H_VISIBLE .U
67+ val vActive = vCount < V_VISIBLE .U
68+ val active = hActive && vActive
6369
64- io.blanking := ! active
70+ io.blanking := ! active
6571
66- val read_address = WireInit (0 .U (32 .W ))
72+ val read_address = WireInit (0 .U (32 .W ))
6773
68- when(active) {
69- read_address := vCount / 2 .U * 320 .U + hCount / 2 .U + 1 .U
70- }.otherwise {
71- read_address := (vCount + 1 .U ) / 2 .U * 320 .U
72- }
74+ when(active) {
75+ read_address := vCount / 2 .U * 320 .U + hCount / 2 .U + 1 .U
76+ }.otherwise {
77+ read_address := (vCount + 1 .U ) / 2 .U * 320 .U
78+ }
7379
74- val color = memory.read(read_address, true .B )
75- val pixel = color(7 , 5 ) ## color(5 ) ## color(4 , 2 ) ## color(2 ) ## color(1 , 0 ) ## color(0 ) ## color(0 )
80+ val color = memory.read(read_address, true .B )
81+ val pixel = color(7 , 5 ) ## color(5 ) ## color(4 , 2 ) ## color(2 ) ## color(1 , 0 ) ## color(0 ) ## color(0 )
7682
77- io.rgb := Mux (active, pixel, 0 .U )
83+ io.rgb := Mux (active, pixel, 0 .U )
84+
85+ }
86+
7887}
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