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‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sim_1/new/tb_Top.v‎

Lines changed: 82 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,91 @@
11
`timescale 1ns / 1ps
2-
32
module tb_Top;
3+
reg clock;
4+
reg reset;
5+
reg io_execute;
6+
reg io_debug_write;
7+
reg [31:0] io_debug_write_address;
8+
reg [31:0] io_debug_write_data;
9+
wire io_hsync;
10+
wire io_vsync;
11+
wire [11:0] io_rgb;
12+
wire io_blanking;
13+
wire [9:0] io_hPos;
14+
wire [9:0] io_vPos;
415

5-
reg clk = 0;
6-
reg btnC = 1;
7-
8-
wire [15:0] led;
9-
wire vgaHSync, vgaVSync;
10-
wire [3:0] vgaRed, vgaGreen, vgaBlue;
11-
12-
always #5 clk = ~clk; // 100MHz
16+
// 25MHz clock: period = 40ns
17+
initial clock = 0;
18+
always #20 clock = ~clock;
19+
Main dut (
20+
.clock (clock),
21+
.reset (reset),
22+
.io_execute (io_execute),
23+
.io_debug_write (io_debug_write),
24+
.io_debug_write_address (io_debug_write_address),
25+
.io_debug_write_data (io_debug_write_data),
1326

14-
Top dut (
15-
.clk (clk),
16-
.btnC (btnC),
17-
.led (led),
18-
.vgaHSync (vgaHSync),
19-
.vgaVSync (vgaVSync),
20-
.vgaRed (vgaRed),
21-
.vgaGreen (vgaGreen),
22-
.vgaBlue (vgaBlue)
27+
.io_hsync (io_hsync),
28+
.io_vsync (io_vsync),
29+
.io_rgb (io_rgb),
30+
.io_blanking (io_blanking),
31+
.io_hPos (io_hPos),
32+
.io_vPos (io_vPos)
2333
);
24-
34+
// Task: rising edge step (matches dut.clock.step(1))
35+
task step;
36+
input integer n;
37+
integer i;
38+
begin
39+
for (i = 0; i < n; i = i + 1) begin
40+
@(posedge clock);
41+
#1; // small delay after edge for signal settling
42+
end
43+
end
44+
endtask
45+
integer cycle;
2546
initial begin
26-
repeat(20) @(posedge clk);
27-
btnC = 0;
28-
#10_000_000; // run for 10ms
47+
// Initial state
48+
reset = 1;
49+
io_execute = 0;
50+
io_debug_write = 0;
51+
io_debug_write_address = 0;
52+
io_debug_write_data = 0;
53+
// Hold reset for 2 cycles
54+
step(2);
55+
reset = 0;
56+
// --- Mirror testbench exactly ---
57+
// dut.io.debug_write.poke(true.B)
58+
io_debug_write = 1;
59+
// poke address=0, data=LUI x2, 4 ; step(1)
60+
io_debug_write_address = 32'd0;
61+
io_debug_write_data = 32'b00000000000000000100_00010_0110111;
62+
step(1);
63+
// poke address=1, data=ADDI x1,x1,8 ; step(1)
64+
io_debug_write_address = 32'd1;
65+
io_debug_write_data = 32'b000000001000_00001_000_00001_0010011;
66+
step(1);
67+
// poke address=2, data=SW x1,0(x2) ; step(1)
68+
io_debug_write_address = 32'd2;
69+
io_debug_write_data = 32'b000000000000_00010_010_00000_0100011;
70+
step(1);
71+
// poke address=3, data=JAL x0,-8 ; step(1)
72+
io_debug_write_address = 32'd3;
73+
io_debug_write_data = 32'b11111111100111111111_00000_1101111;
74+
step(1);
75+
// dut.io.debug_write.poke(false.B) ; step(1)
76+
io_debug_write = 0;
77+
step(1);
78+
// dut.io.execute.poke(true.B) ; step(36)
79+
// Extra cycles needed: each instruction now takes 3 cycles (fetch, wait, execute)
80+
// instead of 2 (fetch, execute), and load/store takes 4 (fetch, wait, execute, complete)
81+
io_execute = 1;
82+
$display("--- Executing for 36 cycles ---");
83+
for (cycle = 0; cycle < 36; cycle = cycle + 1) begin
84+
@(posedge clock); #1;
85+
$display("cycle=%0d rgb=%03x",
86+
cycle, io_rgb);
87+
end
88+
$display("--- Done ---");
2989
$finish;
3090
end
31-
3291
endmodule

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/VGATop.v‎

Lines changed: 39 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,49 +1,64 @@
11
`timescale 1ns / 1ps
2-
32
module VGATop(
4-
input wire clk, // 100MHz
5-
input wire btnC, // reset
3+
input wire clk,
4+
input wire btnC,
5+
input wire RsRx,
6+
output wire RsTx,
7+
output wire [15:0] led,
68
output wire vgaHSync,
79
output wire vgaVSync,
810
output wire [3:0] vgaRed,
911
output wire [3:0] vgaGreen,
1012
output wire [3:0] vgaBlue
1113
);
12-
13-
// -------------------------------------------------------
14-
// Clock divider: 100MHz -> 25MHz (/4 using 2-bit counter)
15-
// -------------------------------------------------------
1614
reg [1:0] clk_div;
1715
always @(posedge clk) begin
1816
if (btnC) clk_div <= 2'h0;
1917
else clk_div <= clk_div + 2'h1;
2018
end
21-
wire clk_25 = clk_div[1]; // toggles at 25MHz
19+
wire clk_25 = clk_div[1];
20+
21+
// Write 0xFFF (white) to VGA address 0 on the first cycle, then stop
22+
reg written;
23+
reg vga_write;
24+
always @(posedge clk_25) begin
25+
if (btnC) begin
26+
written <= 1'b0;
27+
vga_write <= 1'b0;
28+
end else if (!written) begin
29+
vga_write <= 1'b1;
30+
written <= 1'b1;
31+
end else begin
32+
vga_write <= 1'b0;
33+
end
34+
end
2235

23-
// -------------------------------------------------------
24-
// VGA Controller
25-
// -------------------------------------------------------
2636
wire [11:0] rgb;
2737
wire blanking;
2838

2939
VGAController vga (
30-
.clock (clk_25),
31-
.reset (btnC),
32-
.io_address (32'h0),
33-
.io_write (1'b0),
34-
.io_write_value (32'h0),
35-
.io_hsync (vgaHSync),
36-
.io_vsync (vgaVSync),
37-
.io_rgb (rgb),
38-
.io_blanking (blanking),
39-
.io_hPos (), // unused
40-
.io_vPos () // unused
40+
.clock (clk_25),
41+
.reset (btnC),
42+
.io_address (32'h0),
43+
.io_write (vga_write),
44+
.io_write_value (32'hFFF),
45+
.io_hsync (vgaHSync),
46+
.io_vsync (vgaVSync),
47+
.io_rgb (rgb),
48+
.io_blanking (blanking),
49+
.io_hPos (),
50+
.io_vPos ()
4151
);
4252

43-
// rgb[11:8] = red, rgb[7:4] = green, rgb[3:0] = blue
44-
// Blank output when not in active region
4553
assign vgaRed = blanking ? 4'h0 : rgb[11:8];
4654
assign vgaGreen = blanking ? 4'h0 : rgb[7:4];
4755
assign vgaBlue = blanking ? 4'h0 : rgb[3:0];
4856

57+
reg [25:0] alive_counter;
58+
always @(posedge clk_25) begin
59+
if (btnC) alive_counter <= 0;
60+
else alive_counter <= alive_counter + 1;
61+
end
62+
assign led = alive_counter[25:10];
63+
assign RsTx = 1'b1;
4964
endmodule

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 59 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
module Top(
33
input wire clk,
44
input wire btnC,
5-
input wire RsRx,
6-
output wire RsTx,
75
output wire [15:0] led,
86
output wire vgaHSync,
97
output wire vgaVSync,
@@ -22,66 +20,80 @@ module Top(
2220
wire clk_25 = clk_div[1];
2321

2422
// -------------------------------------------------------
25-
// UART program loader
23+
// Hardcoded program loader state machine
24+
// Writes 4 instructions then releases CPU to execute
2625
// -------------------------------------------------------
27-
wire cpu_reset;
28-
wire debug_write;
29-
wire [31:0] debug_write_address;
30-
wire [31:0] debug_write_data;
31-
32-
uart_program_loader loader (
33-
.clk (clk_25),
34-
.rst_n (~btnC),
35-
.rx (RsRx),
36-
.cpu_reset (cpu_reset),
37-
.debug_write (debug_write),
38-
.debug_write_address (debug_write_address),
39-
.debug_write_data (debug_write_data)
40-
);
41-
42-
wire reset = btnC | cpu_reset;
43-
44-
// -------------------------------------------------------
45-
// ce: single pulse per clock cycle - CPU runs at full speed
46-
// but we gate with a slow counter so we can see LEDs
47-
// Counter fires one ce pulse, CPU stage machine runs freely
48-
// -------------------------------------------------------
49-
reg [22:0] ce_counter;
50-
reg ce;
26+
reg reset_reg;
27+
reg debug_write;
28+
reg [31:0] debug_write_address;
29+
reg [31:0] debug_write_data;
30+
reg execute;
31+
reg [2:0] load_state;
5132

5233
always @(posedge clk_25) begin
53-
if (reset) begin
54-
ce_counter <= 23'd0;
55-
ce <= 1'b0;
34+
if (btnC) begin
35+
reset_reg <= 1;
36+
debug_write <= 0;
37+
debug_write_address <= 0;
38+
debug_write_data <= 0;
39+
execute <= 0;
40+
load_state <= 0;
5641
end else begin
57-
ce <= 1'b0;
58-
if (ce_counter == 23'd0) begin
59-
ce <= 1'b1;
60-
end
61-
if (ce_counter == 23'd4_999_999) begin
62-
ce_counter <= 23'd0;
63-
end else begin
64-
ce_counter <= ce_counter + 23'd1;
65-
end
42+
case (load_state)
43+
3'd0: begin
44+
// Release reset, start writing
45+
reset_reg <= 0;
46+
debug_write <= 1;
47+
debug_write_address <= 32'd0;
48+
debug_write_data <= 32'h00004137; // LUI x2, 4
49+
load_state <= 3'd1;
50+
end
51+
3'd1: begin
52+
debug_write_address <= 32'd1;
53+
debug_write_data <= 32'h00808093; // ADDI x1, x1, 8
54+
load_state <= 3'd2;
55+
end
56+
3'd2: begin
57+
debug_write_address <= 32'd2;
58+
debug_write_data <= 32'h00112023; // SW x0, 0(x2)
59+
load_state <= 3'd3;
60+
end
61+
3'd3: begin
62+
debug_write_address <= 32'd3;
63+
debug_write_data <= 32'hFF9FF06F; // JAL x0, -8
64+
load_state <= 3'd4;
65+
end
66+
3'd4: begin
67+
// Stop writing, start executing
68+
debug_write <= 0;
69+
debug_write_address <= 0;
70+
debug_write_data <= 0;
71+
execute <= 1;
72+
load_state <= 3'd5;
73+
end
74+
default: begin
75+
// Stay in execute mode
76+
end
77+
endcase
6678
end
6779
end
6880

6981
// -------------------------------------------------------
7082
// CPU + VGA
7183
// -------------------------------------------------------
72-
wire [31:0] debug_1;
7384
wire [11:0] rgb;
7485
wire blanking;
86+
wire [31:0] debug_1, debug_2;
7587

7688
Main cpu (
7789
.clock (clk_25),
78-
.reset (reset),
79-
.io_execute (ce),
90+
.reset (reset_reg),
91+
.io_execute (execute),
8092
.io_debug_write (debug_write),
8193
.io_debug_write_address (debug_write_address),
8294
.io_debug_write_data (debug_write_data),
8395
.io_debug_1 (debug_1),
84-
.io_busy (),
96+
.io_debug_2 (debug_2),
8597
.io_hsync (vgaHSync),
8698
.io_vsync (vgaVSync),
8799
.io_rgb (rgb),
@@ -93,6 +105,7 @@ module Top(
93105
assign vgaRed = blanking ? 4'h0 : rgb[11:8];
94106
assign vgaGreen = blanking ? 4'h0 : rgb[7:4];
95107
assign vgaBlue = blanking ? 4'h0 : rgb[3:0];
96-
assign led = debug_1[15:0];
97-
assign RsTx = 1'b1;
98-
endmodules
108+
109+
// debug_1 = register 1, debug_2 = program counter
110+
assign led = debug_1[15:0];
111+
endmodule

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