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outercloudstudiooutercloudstudio
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update vivado proejct
1 parent 3e7abb8 commit a5edfef

10 files changed

Lines changed: 320 additions & 71 deletions

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‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml‎

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@@ -1411,11 +1411,11 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Sun Apr 05 17:27:05 UTC 2026</spirit:value>
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<spirit:value>Sun Jun 14 19:05:51 UTC 2026</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:4527b5ca</spirit:value>
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<spirit:value>9:067c9c1a</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v‎

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@@ -2,10 +2,10 @@
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// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
// Date : Sun Apr 5 13:21:14 2026
6-
// Host : arya running 64-bit EndeavourOS Linux
7-
// Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix
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// clk_wiz_0_ clk_wiz_0_sim_netlist.v
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// Date : Sun Jun 14 15:05:51 2026
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// Host : laptop running 64-bit Arch Linux
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// Command : write_verilog -force -mode funcsim
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// /home/liamh/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
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// Design : clk_wiz_0
1010
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
1111
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -32,15 +32,15 @@ module clk_wiz_0
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wire locked;
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wire reset;
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35-
clk_wiz_0_clk_wiz_0_clk_wiz inst
35+
clk_wiz_0_clk_wiz inst
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(.clk_in1(clk_in1),
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.clk_out1(clk_out1),
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.clk_out2(clk_out2),
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.locked(locked),
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.reset(reset));
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endmodule
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43-
module clk_wiz_0_clk_wiz_0_clk_wiz
43+
module clk_wiz_0_clk_wiz
4444
(clk_out1,
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clk_out2,
4646
reset,

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,10 @@
22
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
-- --------------------------------------------------------------------------------
44
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
-- Date : Sun Apr 5 13:21:14 2026
6-
-- Host : arya running 64-bit EndeavourOS Linux
7-
-- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix
8-
-- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl
5+
-- Date : Sun Jun 14 15:05:51 2026
6+
-- Host : laptop running 64-bit Arch Linux
7+
-- Command : write_vhdl -force -mode funcsim
8+
-- /home/liamh/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
99
-- Design : clk_wiz_0
1010
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
1111
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -15,17 +15,17 @@ library IEEE;
1515
use IEEE.STD_LOGIC_1164.ALL;
1616
library UNISIM;
1717
use UNISIM.VCOMPONENTS.ALL;
18-
entity clk_wiz_0_clk_wiz_0_clk_wiz is
18+
entity clk_wiz_0_clk_wiz is
1919
port (
2020
clk_out1 : out STD_LOGIC;
2121
clk_out2 : out STD_LOGIC;
2222
reset : in STD_LOGIC;
2323
locked : out STD_LOGIC;
2424
clk_in1 : in STD_LOGIC
2525
);
26-
end clk_wiz_0_clk_wiz_0_clk_wiz;
26+
end clk_wiz_0_clk_wiz;
2727

28-
architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
28+
architecture STRUCTURE of clk_wiz_0_clk_wiz is
2929
signal clk_in1_clk_wiz_0 : STD_LOGIC;
3030
signal clk_out1_clk_wiz_0 : STD_LOGIC;
3131
signal clk_out2_clk_wiz_0 : STD_LOGIC;
@@ -187,7 +187,7 @@ end clk_wiz_0;
187187

188188
architecture STRUCTURE of clk_wiz_0 is
189189
begin
190-
inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
190+
inst: entity work.clk_wiz_0_clk_wiz
191191
port map (
192192
clk_in1 => clk_in1,
193193
clk_out1 => clk_out1,

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v‎

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Original file line numberDiff line numberDiff line change
@@ -2,10 +2,10 @@
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// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
// --------------------------------------------------------------------------------
44
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
// Date : Sun Apr 5 13:21:14 2026
6-
// Host : arya running 64-bit EndeavourOS Linux
7-
// Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix
8-
// clk_wiz_0_ clk_wiz_0_stub.v
5+
// Date : Sun Jun 14 15:05:51 2026
6+
// Host : laptop running 64-bit Arch Linux
7+
// Command : write_verilog -force -mode synth_stub
8+
// /home/liamh/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
99
// Design : clk_wiz_0
1010
// Purpose : Stub declaration of top-level module interface
1111
// Device : xc7a35tcpg236-1

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,10 @@
22
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
33
-- --------------------------------------------------------------------------------
44
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5-
-- Date : Sun Apr 5 13:21:14 2026
6-
-- Host : arya running 64-bit EndeavourOS Linux
7-
-- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix
8-
-- clk_wiz_0_ clk_wiz_0_stub.vhdl
5+
-- Date : Sun Jun 14 15:05:51 2026
6+
-- Host : laptop running 64-bit Arch Linux
7+
-- Command : write_vhdl -force -mode synth_stub
8+
-- /home/liamh/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
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-- Design : clk_wiz_0
1010
-- Purpose : Stub declaration of top-level module interface
1111
-- Device : xc7a35tcpg236-1

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v‎

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1+
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
2+
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
3+
// --------------------------------------------------------------------------------
4+
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5+
// Date : Sun Jun 14 15:05:51 2026
6+
// Host : laptop running 64-bit Arch Linux
7+
// Command : write_verilog -force -mode synth_stub
8+
// /home/liamh/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
9+
// Design : clk_wiz_0
10+
// Purpose : Stub declaration of top-level module interface
11+
// Device : xc7a35tcpg236-1
12+
// --------------------------------------------------------------------------------
13+
14+
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
15+
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
16+
// Please paste the declaration into a Verilog source file or add the file as an additional source.
17+
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
18+
module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1)
19+
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
20+
/* synthesis syn_force_seq_prim="clk_out1" */
21+
/* synthesis syn_force_seq_prim="clk_out2" */;
22+
output clk_out1 /* synthesis syn_isclock = 1 */;
23+
output clk_out2 /* synthesis syn_isclock = 1 */;
24+
input reset;
25+
output locked;
26+
input clk_in1;
27+
endmodule

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl‎

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1+
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
2+
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
3+
-- --------------------------------------------------------------------------------
4+
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
5+
-- Date : Sun Jun 14 15:05:51 2026
6+
-- Host : laptop running 64-bit Arch Linux
7+
-- Command : write_vhdl -force -mode synth_stub
8+
-- /home/liamh/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
9+
-- Design : clk_wiz_0
10+
-- Purpose : Stub declaration of top-level module interface
11+
-- Device : xc7a35tcpg236-1
12+
-- --------------------------------------------------------------------------------
13+
library IEEE;
14+
use IEEE.STD_LOGIC_1164.ALL;
15+
16+
entity clk_wiz_0 is
17+
Port (
18+
clk_out1 : out STD_LOGIC;
19+
clk_out2 : out STD_LOGIC;
20+
reset : in STD_LOGIC;
21+
locked : out STD_LOGIC;
22+
clk_in1 : in STD_LOGIC
23+
);
24+
25+
attribute CORE_GENERATION_INFO : string;
26+
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
27+
end clk_wiz_0;
28+
29+
architecture stub of clk_wiz_0 is
30+
attribute syn_black_box : boolean;
31+
attribute black_box_pad_pin : string;
32+
attribute syn_black_box of stub : architecture is true;
33+
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1";
34+
begin
35+
end;

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -70,18 +70,18 @@ module Top(
7070
.clock (cpu_clk),
7171
.reset (reset),
7272
.io_execute (execute),
73-
.io_debug_write (debug_write),
74-
.io_debug_write_address (debug_write_address),
75-
.io_debug_write_data (debug_write_data),
76-
.io_debug_1 (debug_1),
77-
.io_debug_2 (debug_2),
78-
.io_hsync (vgaHSync),
79-
.io_vsync (vgaVSync),
73+
.io_flash (debug_write),
74+
.io_flash_address (debug_write_address),
75+
.io_flash_value (debug_write_data),
76+
// .io_debug_1 (debug_1),
77+
// .io_debug_2 (debug_2),
78+
.io_hsync (vga_hsync_int),
79+
.io_vsync (vga_vsync_int),
8080
.io_rgb (rgb),
8181
.io_blanking (blanking),
82-
.io_vga_clk (clk_25),
83-
.io_btns(btns)
84-
82+
.io_vga_clk (clk_25),
83+
.io_btns (btns)
84+
// .io_tx (RsTx)
8585
);
8686

8787
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

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