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Revert "testing vga controller"
This reverts commit b508a58.
1 parent b508a58 commit b3920b0

8 files changed

Lines changed: 206 additions & 151 deletions

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‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/VGATop.v‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,9 @@ module VGATop(
4545
.io_hsync (vgaHSync),
4646
.io_vsync (vgaVSync),
4747
.io_rgb (rgb),
48-
.io_blanking (blanking)
48+
.io_blanking (blanking),
49+
.io_hPos (),
50+
.io_vPos ()
4951
);
5052

5153
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,9 @@ module Top(
6161
.io_hsync (vgaHSync),
6262
.io_vsync (vgaVSync),
6363
.io_rgb (rgb),
64-
.io_blanking (blanking)
64+
.io_blanking (blanking),
65+
.io_hPos (),
66+
.io_vPos ()
6567
);
6668

6769
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
55
<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
66

7-
<Project Product="Vivado" Version="7" Minor="71" Path="C:/Users/outer/OneDrive/Desktop/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr">
7+
<Project Product="Vivado" Version="7" Minor="71" Path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr">
88
<DefaultLaunch Dir="$PRUNDIR"/>
99
<Configuration>
1010
<Option Name="Id" Val="5ccae5db352846dd96f73584352a58b3"/>
@@ -43,7 +43,8 @@
4343
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
4444
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
4545
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
46-
<Option Name="BoardPart" Val=""/>
46+
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
47+
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2025.2/xhub/board_store/xilinx_board_store"/>
4748
<Option Name="ActiveSimSet" Val="sim_1"/>
4849
<Option Name="DefaultLib" Val="xil_defaultlib"/>
4950
<Option Name="ProjectType" Val="Default"/>
@@ -90,85 +91,78 @@
9091
<FileSets Version="1" Minor="32">
9192
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
9293
<Filter Type="Srcs"/>
93-
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
94+
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
9495
<FileInfo>
9596
<Attr Name="AutoDisabled" Val="1"/>
9697
<Attr Name="UsedIn" Val="synthesis"/>
9798
<Attr Name="UsedIn" Val="implementation"/>
9899
<Attr Name="UsedIn" Val="simulation"/>
99100
</FileInfo>
100101
</File>
101-
<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
102+
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
102103
<FileInfo>
103-
<Attr Name="AutoDisabled" Val="1"/>
104104
<Attr Name="UsedIn" Val="synthesis"/>
105105
<Attr Name="UsedIn" Val="implementation"/>
106106
<Attr Name="UsedIn" Val="simulation"/>
107107
</FileInfo>
108108
</File>
109-
<File Path="$PPRDIR/../generated/Decoder.sv">
109+
<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
110110
<FileInfo>
111-
<Attr Name="AutoDisabled" Val="1"/>
112111
<Attr Name="UsedIn" Val="synthesis"/>
113112
<Attr Name="UsedIn" Val="implementation"/>
114113
<Attr Name="UsedIn" Val="simulation"/>
115114
</FileInfo>
116115
</File>
117-
<File Path="$PPRDIR/../generated/Main.sv">
116+
<File Path="$PPRDIR/../generated/Decoder.sv">
118117
<FileInfo>
119-
<Attr Name="AutoDisabled" Val="1"/>
120118
<Attr Name="UsedIn" Val="synthesis"/>
121119
<Attr Name="UsedIn" Val="implementation"/>
122120
<Attr Name="UsedIn" Val="simulation"/>
123121
</FileInfo>
124122
</File>
125-
<File Path="$PPRDIR/../generated/Memory.sv">
123+
<File Path="$PPRDIR/../generated/Main.sv">
126124
<FileInfo>
127-
<Attr Name="AutoDisabled" Val="1"/>
128125
<Attr Name="UsedIn" Val="synthesis"/>
129126
<Attr Name="UsedIn" Val="implementation"/>
130127
<Attr Name="UsedIn" Val="simulation"/>
131128
</FileInfo>
132129
</File>
133-
<File Path="$PPRDIR/../generated/Registers.sv">
130+
<File Path="$PPRDIR/../generated/Memory.sv">
134131
<FileInfo>
135-
<Attr Name="AutoDisabled" Val="1"/>
136132
<Attr Name="UsedIn" Val="synthesis"/>
137133
<Attr Name="UsedIn" Val="implementation"/>
138134
<Attr Name="UsedIn" Val="simulation"/>
139135
</FileInfo>
140136
</File>
141-
<File Path="$PPRDIR/../generated/memory_1024x32.sv">
137+
<File Path="$PPRDIR/../generated/Registers.sv">
142138
<FileInfo>
143-
<Attr Name="AutoDisabled" Val="1"/>
144139
<Attr Name="UsedIn" Val="synthesis"/>
145140
<Attr Name="UsedIn" Val="implementation"/>
146141
<Attr Name="UsedIn" Val="simulation"/>
147142
</FileInfo>
148143
</File>
149-
<File Path="$PSRCDIR/sources_1/new/top.v">
144+
<File Path="$PPRDIR/../generated/VGAController.sv">
150145
<FileInfo>
151-
<Attr Name="AutoDisabled" Val="1"/>
152146
<Attr Name="UsedIn" Val="synthesis"/>
153147
<Attr Name="UsedIn" Val="implementation"/>
154148
<Attr Name="UsedIn" Val="simulation"/>
155149
</FileInfo>
156150
</File>
157-
<File Path="$PPRDIR/../generated/VGAController.sv">
151+
<File Path="$PPRDIR/../generated/memory_1024x32.sv">
158152
<FileInfo>
159153
<Attr Name="UsedIn" Val="synthesis"/>
160154
<Attr Name="UsedIn" Val="implementation"/>
161155
<Attr Name="UsedIn" Val="simulation"/>
162156
</FileInfo>
163157
</File>
164-
<File Path="$PPRDIR/../generated/memory_76800x8.sv">
158+
<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
165159
<FileInfo>
166160
<Attr Name="UsedIn" Val="synthesis"/>
167161
<Attr Name="UsedIn" Val="implementation"/>
168162
<Attr Name="UsedIn" Val="simulation"/>
169163
</FileInfo>
170164
</File>
171-
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
165+
<File Path="$PSRCDIR/sources_1/new/top.v">
172166
<FileInfo>
173167
<Attr Name="UsedIn" Val="synthesis"/>
174168
<Attr Name="UsedIn" Val="implementation"/>
@@ -177,7 +171,8 @@
177171
</File>
178172
<Config>
179173
<Option Name="DesignMode" Val="RTL"/>
180-
<Option Name="TopModule" Val="VGATop"/>
174+
<Option Name="TopModule" Val="Top"/>
175+
<Option Name="TopAutoSet" Val="TRUE"/>
181176
</Config>
182177
</FileSet>
183178
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -235,7 +230,7 @@
235230
</FileSet>
236231
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
237232
<Filter Type="Utils"/>
238-
<File Path="$PSRCDIR/utils_1/imports/synth_1/Top.dcp">
233+
<File Path="$PSRCDIR/utils_1/imports/synth_1/Main.dcp">
239234
<FileInfo>
240235
<Attr Name="UsedIn" Val="synthesis"/>
241236
<Attr Name="UsedIn" Val="implementation"/>
@@ -259,15 +254,18 @@
259254
<Simulator Name="Questa">
260255
<Option Name="Description" Val="Questa Advanced Simulator"/>
261256
</Simulator>
257+
<Simulator Name="Xcelium">
258+
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
259+
</Simulator>
260+
<Simulator Name="VCS">
261+
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
262+
</Simulator>
262263
<Simulator Name="Riviera">
263264
<Option Name="Description" Val="Riviera-PRO Simulator"/>
264265
</Simulator>
265-
<Simulator Name="ActiveHDL">
266-
<Option Name="Description" Val="Active-HDL Simulator"/>
267-
</Simulator>
268266
</Simulators>
269267
<Runs Version="1" Minor="22">
270-
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/Top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
268+
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/Main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
271269
<Strategy Version="1" Minor="2">
272270
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/>
273271
<Step Id="synth_design"/>
@@ -296,7 +294,9 @@
296294
<RQSFiles/>
297295
</Run>
298296
</Runs>
299-
<Board/>
297+
<Board>
298+
<Jumpers/>
299+
</Board>
300300
<DashboardSummary Version="1" Minor="0">
301301
<Dashboards>
302302
<Dashboard Name="default_dashboard">

‎src/main/scala/RISCV/ALU.scala‎

Lines changed: 76 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -4,16 +4,31 @@ import chisel3._
44
import chisel3.util._
55
import _root_.circt.stage.ChiselStage
66

7-
/** @param width
8-
* Bit width (default: 32 bits)
7+
/**
8+
* @param width Bit width (default: 32 bits)
9+
*
10+
* The Arithmetic Logic Unit (ALU) for RISC-V
11+
* Supports: Addition, Multiplication, Comparison, Bitwise operations
12+
*
13+
* I/O:
14+
* operation: 4-bit operation code
15+
* signed: boolean to indicate if operands are signed (Only used for comparisons)
16+
* a: first operand
17+
* b: second operand
18+
* output: result of the operation
919
*
10-
* The Arithmetic Logic Unit (ALU) for RISC-V Supports: Addition, Multiplication, Comparison, Bitwise operations
20+
* Operation Codes:
21+
* 0000: Addition
22+
* 0001: Multiplication
23+
* 0010: Comparison (outputs 3 bits: gt, eq, lt)
24+
* 0011: Bitwise AND
25+
* 0100: Bitwise OR
26+
* 0101: Bitwise XOR
27+
* 0110: Bitwise NOT (outputs NOT a)
28+
* 0111: Logical shift left
29+
* 1000: Logical shift right
30+
* 1001: Arithmetic shift right
1131
*
12-
* I/O: operation: 4-bit operation code signed: boolean to indicate if operands are signed (Only used for comparisons) a: first operand b:
13-
* second operand output: result of the operation
14-
*
15-
* Operation Codes: 0000: Addition 0001: Multiplication 0010: Comparison (outputs 3 bits: gt, eq, lt) 0011: Bitwise AND 0100: Bitwise OR
16-
* 0101: Bitwise XOR 0110: Bitwise NOT (outputs NOT a) 0111: Logical shift left 1000: Logical shift right 1001: Arithmetic shift right
1732
*/
1833
class ALU(val width: Int = 32) extends Module {
1934
val io = IO(new Bundle {
@@ -27,48 +42,60 @@ class ALU(val width: Int = 32) extends Module {
2742
io.output := 0.U;
2843

2944
switch(io.operation) {
30-
is("b0000".U) {
31-
io.output := io.a + io.b; // Addition
32-
}
33-
is("b0001".U) {
34-
io.output := io.a * io.b; // Multiplication
35-
}
36-
is("b0010".U) {
37-
when(io.signed) {
38-
val a_s = io.a.asSInt
39-
val b_s = io.b.asSInt
40-
val gt_s = a_s > b_s
41-
val eq_s = a_s === b_s
42-
val lt_s = a_s < b_s
43-
io.output := Cat(0.U((width - 3).W), gt_s, eq_s, lt_s);
44-
}.otherwise {
45-
val gt = io.a > io.b; // Comparison
46-
val eq = io.a === io.b;
47-
val lt = io.a < io.b;
45+
is("b0000".U) {
46+
io.output := io.a + io.b; // Addition
47+
}
48+
is("b0001".U) {
49+
io.output := io.a * io.b; // Multiplication
50+
}
51+
is("b0010".U) {
52+
when(io.signed) {
53+
val a_s = io.a.asSInt
54+
val b_s = io.b.asSInt
55+
val gt_s = a_s > b_s
56+
val eq_s = a_s === b_s
57+
val lt_s = a_s < b_s
58+
io.output := Cat(0.U((width - 3).W), gt_s, eq_s, lt_s);
59+
} .otherwise {
60+
val gt = io.a > io.b; // Comparison
61+
val eq = io.a === io.b;
62+
val lt = io.a < io.b;
4863

49-
io.output := Cat(0.U((width - 3).W), gt, eq, lt);
50-
}
51-
}
52-
is("b0011".U) {
53-
io.output := io.a & io.b; // Bitwise AND
54-
}
55-
is("b0100".U) {
56-
io.output := io.a | io.b; // Bitwise OR
57-
}
58-
is("b0101".U) {
59-
io.output := io.a ^ io.b; // Bitwise XOR
60-
}
61-
is("b0110".U) {
62-
io.output := ~io.a; // Bitwise NOT
63-
}
64-
is("b0111".U) {
65-
io.output := io.a << io.b(4, 0); // Logical shift left
66-
}
67-
is("b1000".U) {
68-
io.output := io.a >> io.b(4, 0); // Logical shift right
69-
}
70-
is("b1001".U) {
71-
io.output := (io.a.asSInt >> io.b(4, 0)).asUInt // Arithmetic shift right
64+
io.output := Cat(0.U((width - 3).W), gt, eq, lt);
7265
}
66+
}
67+
is("b0011".U) {
68+
io.output := io.a & io.b; // Bitwise AND
69+
}
70+
is("b0100".U) {
71+
io.output := io.a | io.b; // Bitwise OR
72+
}
73+
is("b0101".U) {
74+
io.output := io.a ^ io.b; // Bitwise XOR
75+
}
76+
is("b0110".U) {
77+
io.output := ~io.a; // Bitwise NOT
78+
}
79+
is("b0111".U) {
80+
io.output := io.a << io.b(4,0); // Logical shift left
81+
}
82+
is("b1000".U) {
83+
io.output := io.a >> io.b(4,0); // Logical shift right
84+
}
85+
is("b1001".U) {
86+
io.output := (io.a.asSInt >> io.b(4,0)).asUInt // Arithmetic shift right
87+
}
7388
}
7489
}
90+
91+
object ALU extends App {
92+
ChiselStage.emitSystemVerilogFile(
93+
new ALU(32),
94+
firtoolOpts = Array(
95+
"-disable-all-randomization",
96+
"-strip-debug-info",
97+
"-default-layer-specialization=enable"
98+
),
99+
args = Array("--target-dir", "generated")
100+
)
101+
}

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