Skip to content

Commit b508a58

Browse files
outercloudstudiooutercloudstudio
committed
testing vga controller
1 parent f29d8ef commit b508a58

8 files changed

Lines changed: 151 additions & 206 deletions

File tree

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/VGATop.v‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,7 @@ module VGATop(
4545
.io_hsync (vgaHSync),
4646
.io_vsync (vgaVSync),
4747
.io_rgb (rgb),
48-
.io_blanking (blanking),
49-
.io_hPos (),
50-
.io_vPos ()
48+
.io_blanking (blanking)
5149
);
5250

5351
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -61,9 +61,7 @@ module Top(
6161
.io_hsync (vgaHSync),
6262
.io_vsync (vgaVSync),
6363
.io_rgb (rgb),
64-
.io_blanking (blanking),
65-
.io_hPos (),
66-
.io_vPos ()
64+
.io_blanking (blanking)
6765
);
6866

6967
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
55
<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
66

7-
<Project Product="Vivado" Version="7" Minor="71" Path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr">
7+
<Project Product="Vivado" Version="7" Minor="71" Path="C:/Users/outer/OneDrive/Desktop/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr">
88
<DefaultLaunch Dir="$PRUNDIR"/>
99
<Configuration>
1010
<Option Name="Id" Val="5ccae5db352846dd96f73584352a58b3"/>
@@ -43,8 +43,7 @@
4343
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
4444
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
4545
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
46-
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/>
47-
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../.Xilinx/Vivado/2025.2/xhub/board_store/xilinx_board_store"/>
46+
<Option Name="BoardPart" Val=""/>
4847
<Option Name="ActiveSimSet" Val="sim_1"/>
4948
<Option Name="DefaultLib" Val="xil_defaultlib"/>
5049
<Option Name="ProjectType" Val="Default"/>
@@ -91,78 +90,85 @@
9190
<FileSets Version="1" Minor="32">
9291
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
9392
<Filter Type="Srcs"/>
94-
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
93+
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
9594
<FileInfo>
9695
<Attr Name="AutoDisabled" Val="1"/>
9796
<Attr Name="UsedIn" Val="synthesis"/>
9897
<Attr Name="UsedIn" Val="implementation"/>
9998
<Attr Name="UsedIn" Val="simulation"/>
10099
</FileInfo>
101100
</File>
102-
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
101+
<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
103102
<FileInfo>
103+
<Attr Name="AutoDisabled" Val="1"/>
104104
<Attr Name="UsedIn" Val="synthesis"/>
105105
<Attr Name="UsedIn" Val="implementation"/>
106106
<Attr Name="UsedIn" Val="simulation"/>
107107
</FileInfo>
108108
</File>
109-
<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
109+
<File Path="$PPRDIR/../generated/Decoder.sv">
110110
<FileInfo>
111+
<Attr Name="AutoDisabled" Val="1"/>
111112
<Attr Name="UsedIn" Val="synthesis"/>
112113
<Attr Name="UsedIn" Val="implementation"/>
113114
<Attr Name="UsedIn" Val="simulation"/>
114115
</FileInfo>
115116
</File>
116-
<File Path="$PPRDIR/../generated/Decoder.sv">
117+
<File Path="$PPRDIR/../generated/Main.sv">
117118
<FileInfo>
119+
<Attr Name="AutoDisabled" Val="1"/>
118120
<Attr Name="UsedIn" Val="synthesis"/>
119121
<Attr Name="UsedIn" Val="implementation"/>
120122
<Attr Name="UsedIn" Val="simulation"/>
121123
</FileInfo>
122124
</File>
123-
<File Path="$PPRDIR/../generated/Main.sv">
125+
<File Path="$PPRDIR/../generated/Memory.sv">
124126
<FileInfo>
127+
<Attr Name="AutoDisabled" Val="1"/>
125128
<Attr Name="UsedIn" Val="synthesis"/>
126129
<Attr Name="UsedIn" Val="implementation"/>
127130
<Attr Name="UsedIn" Val="simulation"/>
128131
</FileInfo>
129132
</File>
130-
<File Path="$PPRDIR/../generated/Memory.sv">
133+
<File Path="$PPRDIR/../generated/Registers.sv">
131134
<FileInfo>
135+
<Attr Name="AutoDisabled" Val="1"/>
132136
<Attr Name="UsedIn" Val="synthesis"/>
133137
<Attr Name="UsedIn" Val="implementation"/>
134138
<Attr Name="UsedIn" Val="simulation"/>
135139
</FileInfo>
136140
</File>
137-
<File Path="$PPRDIR/../generated/Registers.sv">
141+
<File Path="$PPRDIR/../generated/memory_1024x32.sv">
138142
<FileInfo>
143+
<Attr Name="AutoDisabled" Val="1"/>
139144
<Attr Name="UsedIn" Val="synthesis"/>
140145
<Attr Name="UsedIn" Val="implementation"/>
141146
<Attr Name="UsedIn" Val="simulation"/>
142147
</FileInfo>
143148
</File>
144-
<File Path="$PPRDIR/../generated/VGAController.sv">
149+
<File Path="$PSRCDIR/sources_1/new/top.v">
145150
<FileInfo>
151+
<Attr Name="AutoDisabled" Val="1"/>
146152
<Attr Name="UsedIn" Val="synthesis"/>
147153
<Attr Name="UsedIn" Val="implementation"/>
148154
<Attr Name="UsedIn" Val="simulation"/>
149155
</FileInfo>
150156
</File>
151-
<File Path="$PPRDIR/../generated/memory_1024x32.sv">
157+
<File Path="$PPRDIR/../generated/VGAController.sv">
152158
<FileInfo>
153159
<Attr Name="UsedIn" Val="synthesis"/>
154160
<Attr Name="UsedIn" Val="implementation"/>
155161
<Attr Name="UsedIn" Val="simulation"/>
156162
</FileInfo>
157163
</File>
158-
<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
164+
<File Path="$PPRDIR/../generated/memory_76800x8.sv">
159165
<FileInfo>
160166
<Attr Name="UsedIn" Val="synthesis"/>
161167
<Attr Name="UsedIn" Val="implementation"/>
162168
<Attr Name="UsedIn" Val="simulation"/>
163169
</FileInfo>
164170
</File>
165-
<File Path="$PSRCDIR/sources_1/new/top.v">
171+
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
166172
<FileInfo>
167173
<Attr Name="UsedIn" Val="synthesis"/>
168174
<Attr Name="UsedIn" Val="implementation"/>
@@ -171,8 +177,7 @@
171177
</File>
172178
<Config>
173179
<Option Name="DesignMode" Val="RTL"/>
174-
<Option Name="TopModule" Val="Top"/>
175-
<Option Name="TopAutoSet" Val="TRUE"/>
180+
<Option Name="TopModule" Val="VGATop"/>
176181
</Config>
177182
</FileSet>
178183
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -230,7 +235,7 @@
230235
</FileSet>
231236
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
232237
<Filter Type="Utils"/>
233-
<File Path="$PSRCDIR/utils_1/imports/synth_1/Main.dcp">
238+
<File Path="$PSRCDIR/utils_1/imports/synth_1/Top.dcp">
234239
<FileInfo>
235240
<Attr Name="UsedIn" Val="synthesis"/>
236241
<Attr Name="UsedIn" Val="implementation"/>
@@ -254,18 +259,15 @@
254259
<Simulator Name="Questa">
255260
<Option Name="Description" Val="Questa Advanced Simulator"/>
256261
</Simulator>
257-
<Simulator Name="Xcelium">
258-
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
259-
</Simulator>
260-
<Simulator Name="VCS">
261-
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
262-
</Simulator>
263262
<Simulator Name="Riviera">
264263
<Option Name="Description" Val="Riviera-PRO Simulator"/>
265264
</Simulator>
265+
<Simulator Name="ActiveHDL">
266+
<Option Name="Description" Val="Active-HDL Simulator"/>
267+
</Simulator>
266268
</Simulators>
267269
<Runs Version="1" Minor="22">
268-
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/Main.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
270+
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/Top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
269271
<Strategy Version="1" Minor="2">
270272
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/>
271273
<Step Id="synth_design"/>
@@ -294,9 +296,7 @@
294296
<RQSFiles/>
295297
</Run>
296298
</Runs>
297-
<Board>
298-
<Jumpers/>
299-
</Board>
299+
<Board/>
300300
<DashboardSummary Version="1" Minor="0">
301301
<Dashboards>
302302
<Dashboard Name="default_dashboard">

‎src/main/scala/RISCV/ALU.scala‎

Lines changed: 49 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -4,31 +4,16 @@ import chisel3._
44
import chisel3.util._
55
import _root_.circt.stage.ChiselStage
66

7-
/**
8-
* @param width Bit width (default: 32 bits)
9-
*
10-
* The Arithmetic Logic Unit (ALU) for RISC-V
11-
* Supports: Addition, Multiplication, Comparison, Bitwise operations
12-
*
13-
* I/O:
14-
* operation: 4-bit operation code
15-
* signed: boolean to indicate if operands are signed (Only used for comparisons)
16-
* a: first operand
17-
* b: second operand
18-
* output: result of the operation
7+
/** @param width
8+
* Bit width (default: 32 bits)
199
*
20-
* Operation Codes:
21-
* 0000: Addition
22-
* 0001: Multiplication
23-
* 0010: Comparison (outputs 3 bits: gt, eq, lt)
24-
* 0011: Bitwise AND
25-
* 0100: Bitwise OR
26-
* 0101: Bitwise XOR
27-
* 0110: Bitwise NOT (outputs NOT a)
28-
* 0111: Logical shift left
29-
* 1000: Logical shift right
30-
* 1001: Arithmetic shift right
10+
* The Arithmetic Logic Unit (ALU) for RISC-V Supports: Addition, Multiplication, Comparison, Bitwise operations
3111
*
12+
* I/O: operation: 4-bit operation code signed: boolean to indicate if operands are signed (Only used for comparisons) a: first operand b:
13+
* second operand output: result of the operation
14+
*
15+
* Operation Codes: 0000: Addition 0001: Multiplication 0010: Comparison (outputs 3 bits: gt, eq, lt) 0011: Bitwise AND 0100: Bitwise OR
16+
* 0101: Bitwise XOR 0110: Bitwise NOT (outputs NOT a) 0111: Logical shift left 1000: Logical shift right 1001: Arithmetic shift right
3217
*/
3318
class ALU(val width: Int = 32) extends Module {
3419
val io = IO(new Bundle {
@@ -42,60 +27,48 @@ class ALU(val width: Int = 32) extends Module {
4227
io.output := 0.U;
4328

4429
switch(io.operation) {
45-
is("b0000".U) {
46-
io.output := io.a + io.b; // Addition
47-
}
48-
is("b0001".U) {
49-
io.output := io.a * io.b; // Multiplication
50-
}
51-
is("b0010".U) {
52-
when(io.signed) {
53-
val a_s = io.a.asSInt
54-
val b_s = io.b.asSInt
55-
val gt_s = a_s > b_s
56-
val eq_s = a_s === b_s
57-
val lt_s = a_s < b_s
58-
io.output := Cat(0.U((width - 3).W), gt_s, eq_s, lt_s);
59-
} .otherwise {
60-
val gt = io.a > io.b; // Comparison
61-
val eq = io.a === io.b;
62-
val lt = io.a < io.b;
30+
is("b0000".U) {
31+
io.output := io.a + io.b; // Addition
32+
}
33+
is("b0001".U) {
34+
io.output := io.a * io.b; // Multiplication
35+
}
36+
is("b0010".U) {
37+
when(io.signed) {
38+
val a_s = io.a.asSInt
39+
val b_s = io.b.asSInt
40+
val gt_s = a_s > b_s
41+
val eq_s = a_s === b_s
42+
val lt_s = a_s < b_s
43+
io.output := Cat(0.U((width - 3).W), gt_s, eq_s, lt_s);
44+
}.otherwise {
45+
val gt = io.a > io.b; // Comparison
46+
val eq = io.a === io.b;
47+
val lt = io.a < io.b;
6348

64-
io.output := Cat(0.U((width - 3).W), gt, eq, lt);
49+
io.output := Cat(0.U((width - 3).W), gt, eq, lt);
50+
}
51+
}
52+
is("b0011".U) {
53+
io.output := io.a & io.b; // Bitwise AND
54+
}
55+
is("b0100".U) {
56+
io.output := io.a | io.b; // Bitwise OR
57+
}
58+
is("b0101".U) {
59+
io.output := io.a ^ io.b; // Bitwise XOR
60+
}
61+
is("b0110".U) {
62+
io.output := ~io.a; // Bitwise NOT
63+
}
64+
is("b0111".U) {
65+
io.output := io.a << io.b(4, 0); // Logical shift left
66+
}
67+
is("b1000".U) {
68+
io.output := io.a >> io.b(4, 0); // Logical shift right
69+
}
70+
is("b1001".U) {
71+
io.output := (io.a.asSInt >> io.b(4, 0)).asUInt // Arithmetic shift right
6572
}
66-
}
67-
is("b0011".U) {
68-
io.output := io.a & io.b; // Bitwise AND
69-
}
70-
is("b0100".U) {
71-
io.output := io.a | io.b; // Bitwise OR
72-
}
73-
is("b0101".U) {
74-
io.output := io.a ^ io.b; // Bitwise XOR
75-
}
76-
is("b0110".U) {
77-
io.output := ~io.a; // Bitwise NOT
78-
}
79-
is("b0111".U) {
80-
io.output := io.a << io.b(4,0); // Logical shift left
81-
}
82-
is("b1000".U) {
83-
io.output := io.a >> io.b(4,0); // Logical shift right
84-
}
85-
is("b1001".U) {
86-
io.output := (io.a.asSInt >> io.b(4,0)).asUInt // Arithmetic shift right
87-
}
8873
}
8974
}
90-
91-
object ALU extends App {
92-
ChiselStage.emitSystemVerilogFile(
93-
new ALU(32),
94-
firtoolOpts = Array(
95-
"-disable-all-randomization",
96-
"-strip-debug-info",
97-
"-default-layer-specialization=enable"
98-
),
99-
args = Array("--target-dir", "generated")
100-
)
101-
}

0 commit comments

Comments
 (0)