fix memory controller and test program

Author: outercloudstudio

src/main/scala/RISCV/Main.scala

@@ -242,10 +242,11 @@ class Main() extends Module {
                     memory.io.address_2 := (registers.io.out_a + decoder.io.immediate) / 4.U + 1.U;
 
                     printf(
-                      "[SW] Rs1: %d Rs2: %d Immediate: %b\n",
+                      "[SW] Rs1: %d Rs2: %d Immediate: %b Raw Address: %b\n",
                       decoder.io.rs1,
                       decoder.io.rs2,
-                      registers.io.out_a + decoder.io.immediate
+                      registers.io.out_a + decoder.io.immediate,
+                      (registers.io.out_a + decoder.io.immediate) / 4.U
                     );
                 }
 

src/main/scala/RISCV/Memory.scala

@@ -32,23 +32,30 @@ class Memory() extends Module {
     io.read_value_1    := 0.U
     io.read_value_2    := 0.U
 
-    val isVGA = io.address_1 > 0b1000000000000.U; 
+    val isVGA = io.address_1 >= 0b1000000000000.U; 
     io.address_vga := Mux(isVGA, io.address_1 - 0b1000000000000.U,0.U);
     io.write_vga   := isVGA && io.write_1
     io.write_value_vga := io.write_value_1
 
+    when(isVGA) {
+        printf(
+            "Writing to VGA! Address: %b Data: %b\n",
+            io.address_1 - 0b1000000000000.U,
+            io.write_value_1
+        );
+    }
 
     io.read_value_1 := memory.readWrite(
         io.address_1,
         io.write_value_1,
-        io.read_1 || io.write_1,
+        (io.read_1 || io.write_1) && !isVGA,
         io.write_1
     )
 
     io.read_value_2 := memory.readWrite(
         io.address_2,
         io.write_value_2,
-        io.read_2 || io.write_2,
+        (io.read_2 || io.write_2) && !isVGA,
         io.write_2
     )
 

src/test/scala/RISCV/MainSpec.scala

@@ -44,22 +44,39 @@ class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
             dut.io.debug_write.poke(true.B)
 
             dut.io.debug_write_address.poke(0.U)
-            dut.io.debug_write_data.poke(0b000000000111_00000_000_00001_0010011.U) // ADDI
+            dut.io.debug_write_data.poke(0b00000000000000000100_00010_0110111L.U) // LUI
             dut.clock.step(1)
 
             dut.io.debug_write_address.poke(1.U)
-            dut.io.debug_write_data.poke(0b0000000_00001_00000_010_00000_0100011.U) // SW
+            dut.io.debug_write_data.poke(0b000000001000_00001_000_00001_0010011L.U) // ADDI
             dut.clock.step(1)
 
             dut.io.debug_write_address.poke(2.U)
-            dut.io.debug_write_data.poke(0b000000000000_00000_010_00010_0000011.U) // LW
+            dut.io.debug_write_data.poke(0b000000000000_00010_010_00000_0100011L.U) // SW
             dut.clock.step(1)
+
+            dut.io.debug_write_address.poke(3.U)
+            dut.io.debug_write_data.poke(0b11111111100111111111_00000_1101111L.U) // JAL
+            dut.clock.step(1)
+            
+
+            // dut.io.debug_write_address.poke(0.U)
+            // dut.io.debug_write_data.poke(0b000000000111_00000_000_00001_0010011.U) // ADDI
+            // dut.clock.step(1)
+
+            // dut.io.debug_write_address.poke(1.U)
+            // dut.io.debug_write_data.poke(0b0000000_00001_00000_010_00000_0100011.U) // SW
+            // dut.clock.step(1)
+
+            // dut.io.debug_write_address.poke(2.U)
+            // dut.io.debug_write_data.poke(0b000000000000_00000_010_00010_0000011.U) // LW
+            // dut.clock.step(1)
 
             dut.io.debug_write.poke(false.B)
             dut.clock.step(1)
 
             dut.io.execute.poke(true.B)
-            dut.clock.step(12)
+            dut.clock.step(24)
         }
   }
 }