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arghunterarghunter
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wth is going on
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‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/README.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/constrs_1/new/master.xdc‎

Lines changed: 17 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -1,52 +1,3 @@
1-
### Clock
2-
#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
3-
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
4-
5-
### Reset (btnC)
6-
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
7-
8-
### VGA Sync
9-
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vgaHSync]
10-
#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vgaVSync]
11-
12-
### VGA Red
13-
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
14-
#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
15-
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
16-
#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
17-
18-
### VGA Green
19-
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
20-
#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
21-
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
22-
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
23-
24-
### VGA Blue
25-
#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
26-
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
27-
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
28-
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
29-
30-
### Configuration
31-
#set_property CONFIG_VOLTAGE 3.3 [current_design]
32-
#set_property CFGBVS VCCO [current_design]
33-
#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
34-
#set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
35-
#set_property CONFIG_MODE SPIx4 [current_design]
36-
37-
38-
39-
40-
41-
42-
43-
44-
45-
46-
47-
48-
49-
501
## Clock
512
set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]
523
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
@@ -76,14 +27,25 @@ set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports {led[13]
7627
set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports {led[14]}]
7728
set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports {led[15]}]
7829

30+
## VGA
31+
set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[0]}]
32+
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[1]}]
33+
set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[2]}]
34+
set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports {vgaRed[3]}]
35+
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[0]}]
36+
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[1]}]
37+
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[2]}]
38+
set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports {vgaGreen[3]}]
39+
set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[0]}]
40+
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[1]}]
41+
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[2]}]
42+
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports {vgaBlue[3]}]
43+
set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports vgaHSync]
44+
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports vgaVSync]
45+
7946
## Configuration
8047
set_property CONFIG_VOLTAGE 3.3 [current_design]
8148
set_property CFGBVS VCCO [current_design]
8249
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
8350
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
84-
set_property CONFIG_MODE SPIx4 [current_design]
85-
86-
87-
88-
89-
51+
set_property CONFIG_MODE SPIx4 [current_design]

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sim_1/new/tb_Top.v‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
`timescale 1ns / 1ps
2+
3+
module tb_Top;
4+
5+
reg clk = 0;
6+
reg btnC = 1;
7+
8+
wire [15:0] led;
9+
wire vgaHSync, vgaVSync;
10+
wire [3:0] vgaRed, vgaGreen, vgaBlue;
11+
12+
always #5 clk = ~clk; // 100MHz
13+
14+
Top dut (
15+
.clk (clk),
16+
.btnC (btnC),
17+
.led (led),
18+
.vgaHSync (vgaHSync),
19+
.vgaVSync (vgaVSync),
20+
.vgaRed (vgaRed),
21+
.vgaGreen (vgaGreen),
22+
.vgaBlue (vgaBlue)
23+
);
24+
25+
initial begin
26+
repeat(20) @(posedge clk);
27+
btnC = 0;
28+
#10_000_000; // run for 10ms
29+
$finish;
30+
end
31+
32+
endmodule

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 58 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,25 @@
11
`timescale 1ns / 1ps
2-
32
module Top(
43
input wire clk,
5-
input wire btnC, // external reset
6-
input wire RsRx, // UART RX
7-
output wire RsTx, // UART TX (unused)
8-
output wire [15:0] led
4+
input wire btnC,
5+
input wire RsRx,
6+
output wire RsTx,
7+
output wire [15:0] led,
8+
output wire vgaHSync,
9+
output wire vgaVSync,
10+
output wire [3:0] vgaRed,
11+
output wire [3:0] vgaGreen,
12+
output wire [3:0] vgaBlue
913
);
10-
11-
wire rst_n = ~btnC;
14+
// -------------------------------------------------------
15+
// Clock divider: 100MHz -> 25MHz
16+
// -------------------------------------------------------
17+
reg [1:0] clk_div;
18+
always @(posedge clk) begin
19+
if (btnC) clk_div <= 2'h0;
20+
else clk_div <= clk_div + 2'h1;
21+
end
22+
wire clk_25 = clk_div[1];
1223

1324
// -------------------------------------------------------
1425
// UART program loader
@@ -19,68 +30,69 @@ module Top(
1930
wire [31:0] debug_write_data;
2031

2132
uart_program_loader loader (
22-
.clk (clk),
23-
.rst_n (rst_n),
33+
.clk (clk_25),
34+
.rst_n (~btnC),
2435
.rx (RsRx),
2536
.cpu_reset (cpu_reset),
2637
.debug_write (debug_write),
2738
.debug_write_address (debug_write_address),
2839
.debug_write_data (debug_write_data)
2940
);
3041

42+
wire reset = btnC | cpu_reset;
43+
3144
// -------------------------------------------------------
32-
// 2-cycle wide enable pulse at ~5Hz
33-
// Only runs when CPU is not being loaded
45+
// ce: single pulse per clock cycle - CPU runs at full speed
46+
// but we gate with a slow counter so we can see LEDs
47+
// Counter fires one ce pulse, CPU stage machine runs freely
3448
// -------------------------------------------------------
35-
reg [23:0] ce_counter;
36-
reg [1:0] ce_phase;
37-
reg ce;
49+
reg [22:0] ce_counter;
50+
reg ce;
3851

39-
always @(posedge clk) begin
40-
if (btnC | cpu_reset) begin
41-
ce_counter <= 24'd0;
42-
ce_phase <= 2'd0;
52+
always @(posedge clk_25) begin
53+
if (reset) begin
54+
ce_counter <= 23'd0;
4355
ce <= 1'b0;
4456
end else begin
45-
case (ce_phase)
46-
2'd0: begin
47-
ce <= 1'b0;
48-
if (ce_counter == 24'd19_999_997) begin
49-
ce_counter <= 24'd0;
50-
ce_phase <= 2'd1;
51-
end else begin
52-
ce_counter <= ce_counter + 24'd1;
53-
end
54-
end
55-
2'd1: begin
56-
ce <= 1'b1;
57-
ce_phase <= 2'd2;
58-
end
59-
2'd2: begin
60-
ce <= 1'b1;
61-
ce_phase <= 2'd0;
62-
end
63-
default: ce_phase <= 2'd0;
64-
endcase
57+
ce <= 1'b0;
58+
if (ce_counter == 23'd0) begin
59+
ce <= 1'b1;
60+
end
61+
if (ce_counter == 23'd4_999_999) begin
62+
ce_counter <= 23'd0;
63+
end else begin
64+
ce_counter <= ce_counter + 23'd1;
65+
end
6566
end
6667
end
6768

6869
// -------------------------------------------------------
69-
// CPU
70+
// CPU + VGA
7071
// -------------------------------------------------------
7172
wire [31:0] debug_1;
73+
wire [11:0] rgb;
74+
wire blanking;
7275

7376
Main cpu (
74-
.clock (clk),
75-
.reset (cpu_reset | btnC),
77+
.clock (clk_25),
78+
.reset (reset),
7679
.io_execute (ce),
7780
.io_debug_write (debug_write),
7881
.io_debug_write_address (debug_write_address),
7982
.io_debug_write_data (debug_write_data),
80-
.io_debug_1 (debug_1)
83+
.io_debug_1 (debug_1),
84+
.io_busy (),
85+
.io_hsync (vgaHSync),
86+
.io_vsync (vgaVSync),
87+
.io_rgb (rgb),
88+
.io_blanking (blanking),
89+
.io_hPos (),
90+
.io_vPos ()
8191
);
8292

83-
assign led = debug_1[15:0];
84-
assign RsTx = 1'b1;
85-
86-
endmodule
93+
assign vgaRed = blanking ? 4'h0 : rgb[11:8];
94+
assign vgaGreen = blanking ? 4'h0 : rgb[7:4];
95+
assign vgaBlue = blanking ? 4'h0 : rgb[3:0];
96+
assign led = debug_1[15:0];
97+
assign RsTx = 1'b1;
98+
endmodules

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/uart_rx.v‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ module uart_rx(
6565
end
6666
START: begin
6767
counter <= counter +1;
68-
if(counter == 433) begin
68+
if(counter == 108) begin
6969
if(!rx_sync_1) begin
7070
counter <= 1;
7171
state <= DATA;
@@ -76,7 +76,7 @@ module uart_rx(
7676
end
7777
DATA: begin
7878
counter <= counter +1;
79-
if(counter == 867) begin
79+
if(counter == 217) begin
8080
counter<=0;
8181
data_packet[bit_idx] <= rx_sync_1;
8282
if(bit_idx == 7) begin

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr‎

Lines changed: 20 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@
6060
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
6161
<Option Name="EnableBDX" Val="FALSE"/>
6262
<Option Name="DSABoardId" Val="basys3"/>
63-
<Option Name="WTXSimLaunchSim" Val="0"/>
63+
<Option Name="WTXSimLaunchSim" Val="5"/>
6464
<Option Name="WTModelSimLaunchSim" Val="0"/>
6565
<Option Name="WTQuestaLaunchSim" Val="0"/>
6666
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -91,36 +91,39 @@
9191
<FileSets Version="1" Minor="32">
9292
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
9393
<Filter Type="Srcs"/>
94-
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
94+
<File Path="$PSRCDIR/sources_1/new/top.v">
9595
<FileInfo>
9696
<Attr Name="AutoDisabled" Val="1"/>
9797
<Attr Name="UsedIn" Val="synthesis"/>
9898
<Attr Name="UsedIn" Val="implementation"/>
9999
<Attr Name="UsedIn" Val="simulation"/>
100100
</FileInfo>
101101
</File>
102-
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
102+
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
103103
<FileInfo>
104+
<Attr Name="AutoDisabled" Val="1"/>
104105
<Attr Name="UsedIn" Val="synthesis"/>
105106
<Attr Name="UsedIn" Val="implementation"/>
106107
<Attr Name="UsedIn" Val="simulation"/>
107108
</FileInfo>
108109
</File>
109-
<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
110+
<File Path="$PSRCDIR/sources_1/new/uart_program_loader.v">
110111
<FileInfo>
112+
<Attr Name="AutoDisabled" Val="1"/>
111113
<Attr Name="UsedIn" Val="synthesis"/>
112114
<Attr Name="UsedIn" Val="implementation"/>
113115
<Attr Name="UsedIn" Val="simulation"/>
114116
</FileInfo>
115117
</File>
116-
<File Path="$PPRDIR/../generated/Decoder.sv">
118+
<File Path="$PSRCDIR/sources_1/new/uart_rx.v">
117119
<FileInfo>
120+
<Attr Name="AutoDisabled" Val="1"/>
118121
<Attr Name="UsedIn" Val="synthesis"/>
119122
<Attr Name="UsedIn" Val="implementation"/>
120123
<Attr Name="UsedIn" Val="simulation"/>
121124
</FileInfo>
122125
</File>
123-
<File Path="$PPRDIR/../generated/Main.sv">
126+
<File Path="$PPRDIR/../generated/Decoder.sv">
124127
<FileInfo>
125128
<Attr Name="UsedIn" Val="synthesis"/>
126129
<Attr Name="UsedIn" Val="implementation"/>
@@ -162,7 +165,7 @@
162165
<Attr Name="UsedIn" Val="simulation"/>
163166
</FileInfo>
164167
</File>
165-
<File Path="$PSRCDIR/sources_1/new/top.v">
168+
<File Path="$PPRDIR/../generated/Main.sv">
166169
<FileInfo>
167170
<Attr Name="UsedIn" Val="synthesis"/>
168171
<Attr Name="UsedIn" Val="implementation"/>
@@ -171,7 +174,8 @@
171174
</File>
172175
<Config>
173176
<Option Name="DesignMode" Val="RTL"/>
174-
<Option Name="TopModule" Val="Top"/>
177+
<Option Name="TopModule" Val="Main"/>
178+
<Option Name="TopAutoSet" Val="TRUE"/>
175179
</Config>
176180
</FileSet>
177181
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -188,11 +192,17 @@
188192
</FileSet>
189193
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
190194
<Filter Type="Srcs"/>
195+
<File Path="$PSRCDIR/sim_1/new/tb_Top.v">
196+
<FileInfo>
197+
<Attr Name="UsedIn" Val="synthesis"/>
198+
<Attr Name="UsedIn" Val="implementation"/>
199+
<Attr Name="UsedIn" Val="simulation"/>
200+
</FileInfo>
201+
</File>
191202
<Config>
192203
<Option Name="DesignMode" Val="RTL"/>
193-
<Option Name="TopModule" Val="VGATop"/>
204+
<Option Name="TopModule" Val="tb_Top"/>
194205
<Option Name="TopLib" Val="xil_defaultlib"/>
195-
<Option Name="TopAutoSet" Val="TRUE"/>
196206
<Option Name="TransportPathDelay" Val="0"/>
197207
<Option Name="TransportIntDelay" Val="0"/>
198208
<Option Name="SelectedSimModel" Val="rtl"/>

‎src/main/scala/RISCV/Main.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ class Main() extends Module {
677677
is("b1101111".U) {
678678
registers.io.write_address := decoder.io.rd;
679679
registers.io.write_enable := true.B;
680-
registers.io.in := program_pointer + 1.U;
680+
registers.io.in := program_pointer + 4.U;
681681

682682
program_pointer := (program_pointer.zext + decoder.io.immediate.asSInt).asUInt;
683683
stage := 0.U;
@@ -695,7 +695,7 @@ class Main() extends Module {
695695

696696
registers.io.write_address := decoder.io.rd;
697697
registers.io.write_enable := true.B;
698-
registers.io.in := program_pointer + 1.U;
698+
registers.io.in := program_pointer + 4.U;
699699

700700
program_pointer := (registers.io.out_a.zext + decoder.io.immediate.asSInt).asUInt;
701701
stage := 0.U;

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