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frame buffer testin
1 parent 8bd3c6f commit ebe353d

3 files changed

Lines changed: 16 additions & 11 deletions

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RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/VGATop.v

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,13 +41,11 @@ module VGATop(
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.reset (btnC),
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.io_address (32'h0),
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.io_write (vga_write),
44-
.io_write_value (32'hFFF),
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.io_write_value (32'hFF),
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.io_hsync (vgaHSync),
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.io_vsync (vgaVSync),
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.io_rgb (rgb),
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.io_blanking (blanking),
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.io_hPos (),
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.io_vPos ()
48+
.io_blanking (blanking)
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);
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5351
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
157-
<File Path="$PPRDIR/../generated/memory_76800x8.sv">
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<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
@@ -169,7 +169,7 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
172-
<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
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<File Path="$PPRDIR/../generated/memory_76800x8.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>

src/main/scala/RISCV/VGAController.scala

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,11 @@ class VGAController extends Module {
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val blanking = Output(Bool())
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})
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31-
val memory = SyncReadMem(1024, UInt(32.W))
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val memory = SyncReadMem(320 * 240, UInt(8.W))
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val hCount = RegInit(0.U(10.W))
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val vCount = RegInit(0.U(10.W))
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36-
val pixel = WireInit(0.U(12.W))
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pixel := memory.read(0.U, true.B)
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when(io.write) {
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memory.write(io.address, io.write_value)
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}
@@ -66,6 +63,16 @@ class VGAController extends Module {
6663

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io.blanking := !active
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66+
val read_address = WireInit(0.U(32.W))
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when(active) {
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read_address := 0.U
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}.otherwise {
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read_address := vCount * 320.U + hCount
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}
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val color = memory.read(read_address, true.B)
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val pixel = color(7, 5) ## color(5) ## color(4, 2) ## color(2) ## color(1, 0) ## color(0) ## color(0)
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io.rgb := Mux(active, pixel, 0.U)
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// io.rgb := Mux(active, 0b111111111111.U, 0.U)
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}

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