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2 parents ee4040c + 9f3f1cc commit f818917

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Lines changed: 1170 additions & 768509 deletions

RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr

Lines changed: 55 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,46 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/UartRx.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/obj_dir/VMain.h">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="IsVisible" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/obj_dir/VMain__pch.h">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="IsVisible" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/obj_dir/VMain__Syms.h">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="IsVisible" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/obj_dir/VMain___024root.h">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="IsVisible" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
@@ -119,7 +159,14 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/ALU.sv">
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<File Path="$PPRDIR/../generated/Core.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/DecodeStage.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
@@ -210,6 +257,13 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/ReadStage.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../generated/Registers.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>

build.sh

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,14 @@ echo "Converting to binary..."
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echo "Converting to hex..."
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python convert.py "$BIN" "$HEX" || exit 1
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echo "Loading program..."
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<<<<<<< HEAD
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python load_program.py "$HEX" --port /dev/ttyUSB1
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echo "Cleaning up..."
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rm -f "$OBJ" "$ELF" "$BIN" #"$HEX"
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echo "Done."
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=======
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python load_program.py "$HEX" --port /dev/ttyUSB3
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echo "Cleaning up..."
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rm -f "$OBJ" "$ELF" "$BIN" #"$HEX"
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echo "Done."
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>>>>>>> 9f3f1ccb74f58cfae7e2055ad46a2933e7b06a25

disabled-tests/MainSpec.scala

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
package RISCV
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import chisel3._
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import chisel3.simulator.scalatest.ChiselSim
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import org.scalatest.freespec.AnyFreeSpec
6+
import org.scalatest.matchers.must.Matchers
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import scala.io.Source
8+
import java.nio.file.{Files, Paths}
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import java.nio.ByteBuffer
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import chisel3.simulator.PeekPokeAPI.TestableRecord
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class MainSpec extends AnyFreeSpec with Matchers with ChiselSim {
13+
"Main should execute Store and Load Instructions correctly" in {
14+
simulate(new Main()) { dut =>
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// Load hex file, one instruction per line
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val instructions = Source
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.fromFile("./programs/hello.hex")
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.getLines()
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.filter(_.trim.nonEmpty)
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.map(line => java.lang.Long.parseLong(line.trim, 16))
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.toSeq
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dut.io.debug_write.poke(true.B)
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instructions.zipWithIndex.foreach { case (instr, idx) =>
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dut.io.debug_write_address.poke(idx.U)
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dut.io.debug_write_data.poke(instr.U(32.W))
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dut.clock.step(1)
29+
}
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dut.io.debug_write.poke(false.B)
32+
dut.clock.step(1)
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dut.io.execute.poke(true.B)
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dut.clock.step(64)
36+
}
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}
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// "Main should execute Store and Load Instructions correctly" in {
40+
// simulate(new Main()) { dut =>
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// dut.io.debug_write.poke(true.B)
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// dut.io.debug_write_address.poke(0.U)
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// dut.io.debug_write_data.poke(0x00004137L.U)
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// dut.clock.step(1)
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// dut.io.debug_write_address.poke(1.U)
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// dut.io.debug_write_data.poke(0x000041b7L.U)
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// dut.clock.step(1)
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// dut.io.debug_write_address.poke(2.U)
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// dut.io.debug_write_data.poke(0x00408093L.U)
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// dut.clock.step(1)
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// dut.io.debug_write_address.poke(3.U)
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// dut.io.debug_write_data.poke(0x00218133L.U)
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// dut.clock.step(1)
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// dut.io.debug_write_address.poke(4.U)
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// dut.io.debug_write_data.poke(0x00110023L.U)
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// dut.clock.step(1)
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// dut.io.debug_write_address.poke(5.U)
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// dut.io.debug_write_data.poke(0xff5ff06fL.U)
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// dut.clock.step(1)
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// // dut.io.debug_write_address.poke(0.U)
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// // dut.io.debug_write_data.poke(0b000000000111_00000_000_00001_0010011.U) // ADDI
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// // dut.clock.step(1)
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// // dut.io.debug_write_address.poke(1.U)
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// // dut.io.debug_write_data.poke(0b0000000_00001_00000_010_00000_0100011.U) // SW
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// // dut.clock.step(1)
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// // dut.io.debug_write_address.poke(2.U)
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// // dut.io.debug_write_data.poke(0b000000000000_00000_010_00010_0000011.U) // LW
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// // dut.clock.step(1)
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// dut.io.debug_write.poke(false.B)
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// dut.clock.step(1)
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// dut.io.execute.poke(true.B)
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// dut.clock.step(24)
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// }
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// }
86+
}

programs/hello.c

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ int main() {
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int ballY = 120;
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int dX = 1;
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int dY = 1;
42-
42+
4343
for (int i = 0; i < 320; i++) {
4444
frame[i] = 0xFF;
4545
frame[239 * 320 + i] = 0xFF;
@@ -133,6 +133,13 @@ int main() {
133133
for (int y = -20; y <= 20; y++) {
134134
frame[320 * (paddY2 + y) + 299 + x] = 0xE0;
135135
}
136+
<<<<<<< HEAD
137+
=======
138+
}
139+
140+
for (int i = 0; i < 8000; i++) {
141+
__asm__ volatile("nop");
142+
>>>>>>> 9f3f1ccb74f58cfae7e2055ad46a2933e7b06a25
136143
}
137144
*uart_tx = 'a';
138145
while (*timer - ctime < 8000) {

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