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Emit program counter
1 parent d7266c5 commit 3d8ad93

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src/main/scala/main/Main.scala

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@@ -7,6 +7,7 @@ import _root_.circt.stage.ChiselStage
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object Main extends App {
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emitVerilog(new Alu(), Array("--target-dir", "generated"));
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emitVerilog(new Lsu(), Array("--target-dir", "generated"));
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emitVerilog(new ProgramCounter(), Array("--target-dir", "generated"));
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test(new Lsu) { dut =>
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dut.io.write.poke(true.B);

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