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Commit 47c5d22

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Reduce delay between idle and read start by one cycle
1 parent e979cf2 commit 47c5d22

2 files changed

Lines changed: 6 additions & 8 deletions

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src/main/scala/main/Core.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ class Core extends Module {
5050
printf(p"\n\t\tdispatcher_read_ready=${dispatcher.io.read_ready}");
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printf(p"\n\t\tdebug_dispatcher_opcode=${io.debug_dispatcher_opcode}");
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printf(p"\n\t\tdebug_dispatcher_program_pointer=${io.debug_dispatcher_program_pointer}");
53+
printf(p"\n\t\texecute=${io.execute}");
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printf(p"\n\n");
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}
5556

src/main/scala/main/Dispatcher.scala

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,9 @@ class Dispatcher extends Module {
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val dst_register = Output(Register());
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val program_pointer = Output(UInt(8.W));
2323
});
24-
25-
val read_requested = RegInit(0.U(8.W));
26-
io.read_requested := read_requested;
27-
val read_program_pointer = RegInit(0.U(8.W));
28-
io.read_program_pointer := read_program_pointer;
24+
25+
io.read_program_pointer := io.thread_program_pointer;
26+
io.read_requested := false.B;
2927

3028
val opcode_loaded = RegInit(false.B);
3129
io.opcode_loaded := opcode_loaded;
@@ -42,8 +40,7 @@ class Dispatcher extends Module {
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printf(p"\t[Dispatcher]=====");
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printf(p"\n\t\tMarked read requested!\n\n");
4442

45-
read_program_pointer := io.thread_program_pointer;
46-
read_requested := true.B;
43+
io.read_requested := true.B;
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}
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4946
when(io.read_ready) {
@@ -90,6 +87,6 @@ class Dispatcher extends Module {
9087

9188
program_pointer := io.read_program_pointer;
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93-
read_requested := false.B;
90+
io.read_requested := false.B;
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}
9592
}

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