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outercloudstudiooutercloudstudio
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load almost working
1 parent 224f598 commit 6f17a7b

7 files changed

Lines changed: 105 additions & 82 deletions

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‎README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ The instruction set is 24 bits wide. 8 for opcode and 16 additional bits for imm
3434
`00001` + target --> moves immediate into register
3535
`00010` + src/dst --> moves value in register to register
3636
- load
37-
`00011` + src/dst --> takes address from register and loads memory into other register
37+
`00011` + src/dst --> takes address from register and loads memory into other register. The src and dst registers must not be the same register.
3838
- add
3939
`00100` + src/dst --> add value in src to dst and store in dst
4040
- mul

src/test/scala/main/LsuTest.scala renamed to src/main/disabled-tests/LsuTest.scala

File renamed without changes.

‎src/main/scala/main/Core.scala‎

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,6 @@ class Core extends Module {
1414

1515
val debug_dispatcher_opcode = Output(Operation());
1616
val debug_dispatcher_program_pointer = Output(UInt(8.W));
17-
18-
val debug_thread_debug_output = Output(UInt(8.W));
1917
});
2018

2119
val memory = Module(new Memory());
@@ -33,6 +31,20 @@ class Core extends Module {
3331
.readPorts(2)
3432
.address := 3.U * dispatcher.io.read_program_pointer + 2.U;
3533

34+
memory.io.readPorts(3).enable := thread.io.read_requested;
35+
memory.io
36+
.readPorts(3)
37+
.address := thread.io.read_address;
38+
memory.io.readPorts(4).enable := thread.io.read_requested;
39+
memory.io
40+
.readPorts(4)
41+
.address := thread.io.read_address + 1.U;
42+
43+
thread.io.read_data := memory.io.readPorts(4).data ## memory.io.readPorts(3).data;
44+
45+
val thread_read_ready_delayed = RegNext(thread.io.read_requested, false.B);
46+
thread.io.read_ready := thread_read_ready_delayed;
47+
3648
memory.io.writePorts(0).enable := io.debug_memory_write;
3749
memory.io.writePorts(0).address := io.debug_memory_write_address * 3.U;
3850
memory.io.writePorts(0).data := io.debug_memory_write_data_0;
@@ -46,8 +58,8 @@ class Core extends Module {
4658
dispatcher.io.thread_requesting_opcode := thread.io.idle && io.execute;
4759
dispatcher.io.thread_program_pointer := thread.io.program_pointer;
4860

49-
val read_ready_delayed = RegNext(dispatcher.io.read_requested, false.B);
50-
dispatcher.io.read_ready := read_ready_delayed;
61+
val dispatcher_read_ready_delayed = RegNext(dispatcher.io.read_requested, false.B);
62+
dispatcher.io.read_ready := dispatcher_read_ready_delayed;
5163
dispatcher.io.read_opcode := memory.io.readPorts(0).data(7, 0);
5264
dispatcher.io.read_immediate_l := memory.io.readPorts(1).data(7, 0);
5365
dispatcher.io.read_immediate_u := memory.io.readPorts(2).data(7, 0);
@@ -83,6 +95,4 @@ class Core extends Module {
8395
dispatcher.io.read_immediate_l
8496
);
8597
thread.io.operation_loaded := dispatcher.io.opcode_loaded;
86-
87-
io.debug_thread_debug_output := thread.io.debug_output;
8898
}

‎src/main/scala/main/Lsu.scala‎

Lines changed: 21 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3,35 +3,35 @@ import chisel3.util._
33
import _root_.circt.stage.ChiselStage
44

55
object LsuState extends ChiselEnum {
6-
val Idle, Requesting = Value
6+
val Idle, Requesting, Done = Value
77
}
88

99
class Lsu extends Module {
1010
val io = IO(new Bundle {
1111
val read = Input(Bool());
1212
val write = Input(Bool());
1313

14-
val address = Input(UInt(8.W));
15-
val data = Input(UInt(8.W));
14+
val address = Input(UInt(16.W));
15+
val data = Input(UInt(16.W));
1616

1717
val read_requested = Output(Bool());
18-
val read_address = Output(UInt(8.W));
18+
val read_address = Output(UInt(16.W));
1919
val read_ready = Input(Bool());
20-
val read_data = Input(UInt(8.W));
20+
val read_data = Input(UInt(16.W));
2121

2222
val write_requested = Output(Bool());
23-
val write_data = Output(UInt(8.W));
24-
val write_address = Output(UInt(8.W));
23+
val write_data = Output(UInt(16.W));
24+
val write_address = Output(UInt(16.W));
2525
val write_ready = Input(Bool());
2626

2727
val state = Output(LsuState());
28-
val output = Output(UInt(8.W));
28+
val output = Output(UInt(16.W));
2929
})
3030

3131
val state = RegInit(LsuState.Idle);
3232
io.state := state;
3333

34-
val output = RegInit(0.U(8.W));
34+
val output = RegInit(0.U(16.W));
3535
io.output := output;
3636

3737
val read_requested = RegInit(false.B);
@@ -43,10 +43,10 @@ class Lsu extends Module {
4343
val write_requested = RegInit(false.B);
4444
io.write_requested := write_requested;
4545

46-
val write_address = RegInit(0.U(8.W));
46+
val write_address = RegInit(0.U(16.W));
4747
io.write_address := write_address;
4848

49-
val write_data = RegInit(0.U(8.W));
49+
val write_data = RegInit(0.U(16.W));
5050
io.write_data := write_data;
5151

5252
when(io.read) {
@@ -59,11 +59,15 @@ class Lsu extends Module {
5959

6060
is(LsuState.Requesting) {
6161
when(io.read_ready) {
62-
state := LsuState.Idle;
62+
state := LsuState.Done;
6363
read_requested := false.B;
6464
output := io.read_data;
6565
}
6666
}
67+
68+
is(LsuState.Done) {
69+
state := LsuState.Idle;
70+
}
6771
}
6872
}
6973

@@ -78,10 +82,14 @@ class Lsu extends Module {
7882

7983
is(LsuState.Requesting) {
8084
when(io.write_ready) {
81-
state := LsuState.Idle;
85+
state := LsuState.Done;
8286
write_requested := false.B;
8387
}
8488
}
89+
90+
is(LsuState.Done) {
91+
state := LsuState.Idle;
92+
}
8593
}
8694
}
8795
}

‎src/main/scala/main/Memory.scala‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,15 @@ import chisel3.util._
33
import _root_.circt.stage.ChiselStage
44

55
class Memory extends Module {
6-
val io = IO(new SRAMInterface(1024, UInt(8.W), 3, 3, 0));
6+
val io = IO(new SRAMInterface(1024, UInt(8.W), 5, 3, 0));
77

8-
val memory = SRAM(1024, UInt(8.W), 3, 3, 0);
8+
val memory = SRAM(1024, UInt(8.W), 5, 3, 0);
99

1010
io.readPorts(0) <> memory.readPorts(0);
1111
io.readPorts(1) <> memory.readPorts(1);
1212
io.readPorts(2) <> memory.readPorts(2);
13+
io.readPorts(3) <> memory.readPorts(3);
14+
io.readPorts(4) <> memory.readPorts(4);
1315

1416
io.writePorts(0) <> memory.writePorts(0);
1517
io.writePorts(1) <> memory.writePorts(1);

‎src/main/scala/main/Thread.scala‎

Lines changed: 58 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,11 @@ class Thread extends Module {
1414
val program_pointer = Output(UInt(8.W));
1515
val end_of_program = Output(Bool());
1616
val idle = Output(Bool());
17-
val debug_output = Output(UInt(8.W));
17+
18+
val read_requested = Output(Bool());
19+
val read_address = Output(UInt(16.W));
20+
val read_ready = Input(Bool());
21+
val read_data = Input(UInt(16.W));
1822
})
1923

2024
val program_pointer = Module(new ProgramPointer())
@@ -76,13 +80,18 @@ class Thread extends Module {
7680
alu.io.rs := 0.U(8.W);
7781
alu.io.rt := 0.U(8.W);
7882

79-
io.debug_output := alu.io.output;
83+
val lsu = Module(new Lsu())
84+
lsu.io.read := false.B;
85+
lsu.io.write := false.B
86+
lsu.io.address := 0.U;
87+
lsu.io.data := 0.U;
88+
89+
lsu.io.read_ready := io.read_ready;
90+
lsu.io.read_data := io.read_data;
91+
io.read_address := lsu.io.read_address;
92+
io.read_requested := lsu.io.read_requested;
8093

81-
// val lsu = Module(new Lsu())
82-
// lsu.io.read := false.B;
83-
// lsu.io.write := false.B
84-
// lsu.io.address := 0.U;
85-
// lsu.io.data := 0.U;
94+
lsu.io.write_ready := false.B;
8695

8796
val executing_load_write = RegInit(false.B);
8897
val load_write_operation = RegInit(Operation.NoOp);
@@ -184,65 +193,59 @@ class Thread extends Module {
184193
io.idle := false.B;
185194
}
186195

187-
// when(
188-
// io.operation === Operation.Write || io.operation === Operation.Load && !executing_load_write
189-
// ) {
190-
// io.idle := false.B;
191-
// executing_load_write := true.B;
192-
193-
// val operation = WireInit(Operation.NoOp);
194-
// val address = WireInit(0.U(8.W));
195-
// val value = WireInit(0.U(8.W));
196-
197-
// when(executing_load_write) {
198-
// operation := load_write_operation;
199-
// address := load_write_address;
200-
// value := write_value;
201-
// }.otherwise {
202-
// load_write_operation := io.operation;
203-
// operation := io.operation;
204-
205-
// load_write_address := io.immediate;
206-
// address := io.immediate;
207-
208-
// switch(io.src_register) {
209-
// is(Register.A) {
210-
// value := register_a;
211-
// write_value := register_a;
212-
// }
213-
// is(Register.B) {
214-
// value := register_b;
215-
// write_value := register_b;
216-
// }
217-
// is(Register.C) {
218-
// value := register_c;
219-
// write_value := register_c;
220-
// }
221-
// }
222-
// }
223-
224-
// lsu.io.write := operation === Operation.Write;
225-
// lsu.io.read := operation === Operation.Load;
226-
227-
// // when(io.operation)
228-
229-
// when(executing_load_write) {}
230-
// }
196+
when(
197+
io.operation === Operation.Load
198+
) {
199+
io.idle := false.B;
200+
201+
lsu.io.read := true.B;
202+
203+
switch(src_register) {
204+
is(Register.A) {
205+
lsu.io.address := register_a;
206+
}
207+
is(Register.B) {
208+
lsu.io.address := register_b;
209+
}
210+
is(Register.C) {
211+
lsu.io.address := register_c;
212+
}
213+
}
214+
215+
switch(dst_register) {
216+
is(Register.A) {
217+
register_a := lsu.io.output
218+
}
219+
is(Register.B) {
220+
register_b := lsu.io.output
221+
}
222+
is(Register.C) {
223+
register_c := lsu.io.output
224+
}
225+
}
226+
227+
when(lsu.io.state === LsuState.Done) {
228+
program_pointer.io.update := true.B;
229+
program_pointer.io.branch := false.B;
230+
}
231+
}
231232
}
232233

233234
when(true.B) {
234235
printf(p"\t[Thread]=====");
235-
printf(p"\n\t\tio.operation=${io.operation}");
236-
printf(p"\n\t\tio.operation_pointer=${io.operation_pointer}");
237-
printf(p"\n\t\tio.operation_loaded=${io.operation_loaded}");
236+
printf(p"\n\t\toperation=${operation}");
237+
printf(p"\n\t\toperation_pointer=${operation_pointer}");
238+
printf(p"\n\t\toperation_loaded=${operation_loaded}");
238239
printf(p"\n\t\tprogram_pointer=${program_pointer.io.pointer}");
239240
printf(p"\n\t\tio.idle=${io.idle}");
240-
printf(p"\n\t\tio.debug_output=${io.debug_output}");
241241
printf(p"\n\t\ta=${register_a}");
242242
printf(p"\n\t\tb=${register_b}");
243243
printf(p"\n\t\tc=${register_c}");
244244
printf(p"\n\t\tSrc Register=${io.src_register}");
245245
printf(p"\n\t\tDst Register=${io.dst_register}");
246+
printf(p"\n\t\tRead requested=${io.read_requested}");
247+
printf(p"\n\t\tRead ready=${io.read_ready}");
248+
printf(p"\n\t\tLsu state=${lsu.io.state}");
246249
printf(p"\n\n");
247250
}
248251
}

‎src/test/scala/main/CoreTest.scala‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,24 +8,24 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
88
dut.io.debug_memory_write.poke(true.B);
99
dut.io.debug_memory_write_address.poke(0.U(8.W));
1010
dut.io.debug_memory_write_data_0.poke(0b00001010.U(8.W));
11-
dut.io.debug_memory_write_data_1.poke(0b01000000.U(8.W));
11+
dut.io.debug_memory_write_data_1.poke(0b00011110.U(8.W));
1212
dut.io.debug_memory_write_data_2.poke(0b00000000.U(8.W));
1313

1414
println("[CoreTest]=====");
1515
dut.clock.step(1);
1616

1717
dut.io.debug_memory_write.poke(true.B);
1818
dut.io.debug_memory_write_address.poke(1.U(8.W));
19-
dut.io.debug_memory_write_data_0.poke(0b00001000.U(8.W));
20-
dut.io.debug_memory_write_data_1.poke(0b00100010.U(8.W));
19+
dut.io.debug_memory_write_data_0.poke(0b00011000.U(8.W));
20+
dut.io.debug_memory_write_data_1.poke(0b00000010.U(8.W));
2121
dut.io.debug_memory_write_data_2.poke(0b00000000.U(8.W));
2222

2323
println("[CoreTest]=====");
2424
dut.clock.step(1);
2525

2626
dut.io.debug_memory_write.poke(true.B);
27-
dut.io.debug_memory_write_address.poke(2.U(8.W));
28-
dut.io.debug_memory_write_data_0.poke(0b00100000.U(8.W));
27+
dut.io.debug_memory_write_address.poke(10.U(8.W));
28+
dut.io.debug_memory_write_data_0.poke(0b00000101.U(8.W));
2929
dut.io.debug_memory_write_data_1.poke(0b00000000.U(8.W));
3030
dut.io.debug_memory_write_data_2.poke(0b00000000.U(8.W));
3131

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