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Close to updating program counter
1 parent 8430435 commit 7d61729

5 files changed

Lines changed: 38 additions & 40 deletions

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src/main/scala/main/Alu.scala

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,11 @@ import chisel3._
22
import chisel3.util._
33
import _root_.circt.stage.ChiselStage
44

5-
object AluOperation extends ChiselEnum {
6-
val Add, Sub, Mul, Div = Value
7-
}
8-
95
class Alu extends Module {
106
val io = IO(new Bundle {
117
val execute = Input(Bool());
128

13-
val operation = Input(AluOperation());
9+
val operation = Input(Operation());
1410
val compare = Input(Bool());
1511

1612
val rs = Input(UInt(8.W));
@@ -30,19 +26,19 @@ class Alu extends Module {
3026
io.output := Cat(0.U(5.W), gt, eq, lt);
3127
}.otherwise {
3228
switch(io.operation) {
33-
is(AluOperation.Add) {
29+
is(Operation.Add) {
3430
io.output := io.rs + io.rt;
3531
}
3632

37-
is(AluOperation.Sub) {
33+
is(Operation.Sub) {
3834
io.output := io.rs - io.rt;
3935
}
4036

41-
is(AluOperation.Mul) {
37+
is(Operation.Mul) {
4238
io.output := io.rs * io.rt;
4339
}
4440

45-
is(AluOperation.Div) {
41+
is(Operation.Div) {
4642
io.output := io.rs / io.rt;
4743
}
4844
}

src/main/scala/main/Core.scala

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@ class Core extends Module {
1010

1111
val debug_dispatcher_opcode = Output(Operation());
1212
val debug_dispatcher_program_pointer = Output(UInt(8.W));
13+
14+
val debug_thread_debug_output = Output(UInt(8.W));
1315
});
1416

1517
val memory = Module(new Memory());
@@ -30,12 +32,12 @@ class Core extends Module {
3032
dispatcher.io.read_ready := read_ready_delayed;
3133
dispatcher.io.read_opcode := Operation.safe(memory.io.readPorts(0).data(3, 0))._1;
3234

33-
// when(true.B) {
34-
// printf(p"\t[Core]=====");
35-
// printf(p"\n\tdebug.thread_requesting_opcode=${io.debug_dispatcher_thread_requesting_opcode}");
36-
// printf(p"\n\tdispatcher.read_requested=${dispatcher.io.read_requested}");
37-
// printf(p"\n\tread_ready_delayed=${read_ready_delayed}\n\n");
38-
// }
35+
when(true.B) {
36+
printf(p"\t[Core]=====");
37+
printf(p"\n\tdebug_dispatcher_opcode=${io.debug_dispatcher_opcode}");
38+
printf(p"\n\tdebug_dispatcher_program_pointer=${io.debug_dispatcher_program_pointer}");
39+
printf(p"\n\n");
40+
}
3941

4042
io.debug_dispatcher_opcode := dispatcher.io.opcode;
4143
io.debug_dispatcher_program_pointer := dispatcher.io.program_pointer;
@@ -45,4 +47,6 @@ class Core extends Module {
4547
thread.io.operation := dispatcher.io.opcode;
4648
thread.io.immediate_a := 2.U(8.W);
4749
thread.io.immediate_b := 3.U(8.W);
50+
51+
io.debug_thread_debug_output := thread.io.debug_output;
4852
}

src/main/scala/main/Thread.scala

Lines changed: 8 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -26,10 +26,13 @@ class Thread extends Module {
2626

2727
val alu = Module(new Alu())
2828
alu.io.execute := false.B;
29-
alu.io.operation := AluOperation.Add;
29+
alu.io.operation := operation;
3030
alu.io.compare := false.B;
31-
alu.io.rs := 0.U(8.W);
32-
alu.io.rt := 0.U(8.W);
31+
alu.io.rs := immediate_a;
32+
alu.io.rt := immediate_b;
33+
34+
io.debug_output := alu.io.output;
35+
3336
// val lsu = Module(new Lsu())
3437

3538
val program_counter = Module(new ProgramCounter())
@@ -41,8 +44,6 @@ class Thread extends Module {
4144
program_counter.io.target_nzp := 0.U(3.W);
4245

4346
io.program_pointer := program_counter.io.program_counter;
44-
45-
io.debug_output := 0.U(8.W);
4647

4748
io.end_of_program := end_of_program;
4849
io.idle := idle;
@@ -54,26 +55,9 @@ class Thread extends Module {
5455

5556
when(operation === Operation.Add || operation === Operation.Sub || operation === Operation.Mul || operation === Operation.Div) {
5657
alu.io.execute := true.B;
57-
58-
switch(operation) {
59-
is (Operation.Add) {
60-
alu.io.operation := AluOperation.Add;
61-
}
62-
is (Operation.Sub) {
63-
alu.io.operation := AluOperation.Sub;
64-
}
65-
is (Operation.Mul) {
66-
alu.io.operation := AluOperation.Mul;
67-
}
68-
is (Operation.Div) {
69-
alu.io.operation := AluOperation.Div;
70-
}
71-
}
7258

73-
alu.io.rs := io.immediate_a;
74-
alu.io.rt := io.immediate_b;
75-
76-
io.debug_output := alu.io.output;
59+
// program_counter.io.update := true.B;
60+
// program_counter.io.branch := false.B;
7761
}
7862
}
7963
}

src/test/scala/main/AluTest.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ class AluTest extends AnyFlatSpec with ChiselScalatestTester {
66
"Alu Add" should "work" in {
77
test(new Alu) { dut =>
88
dut.io.execute.poke(true.B);
9-
dut.io.operation.poke(AluOperation.Add);
9+
dut.io.operation.poke(Operation.Add);
1010
dut.io.compare.poke(false.B);
1111
dut.io.rs.poke(2.U);
1212
dut.io.rt.poke(3.U);

src/test/scala/main/CoreTest.scala

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,10 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
1010
dut.io.debug_memory_write_data.poke(1.U(8.W));
1111

1212
dut.clock.step(1);
13+
14+
// dut.io.debug_memory_write.poke(true.B);
15+
// dut.io.debug_memory_write_address.poke(1.U(8.W));
16+
// dut.io.debug_memory_write_data.poke(2.U(8.W));
1317

1418
dut.clock.step(1);
1519

@@ -19,6 +23,16 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
1923

2024
dut.io.debug_dispatcher_opcode.expect(Operation.Add);
2125
dut.io.debug_dispatcher_program_pointer.expect(0.U(8.W));
26+
27+
dut.clock.step(1);
28+
29+
dut.io.debug_thread_debug_output.expect(5.U(8.W));
30+
31+
dut.clock.step(1);
32+
33+
dut.clock.step(1);
34+
35+
dut.clock.step(1);
2236
}
2337
}
2438
}

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