@@ -8,15 +8,13 @@ class Core extends Module {
88 val debug_memory_write_address = Input (UInt (8 .W ));
99 val debug_memory_write_data = Input (UInt (8 .W ));
1010
11- val debug_dispatcher_thread_requesting_opcode = Input (Bool ());
12- val debug_dispatcher_thread_program_pointer = Input (UInt (8 .W ));
13-
1411 val debug_dispatcher_opcode = Output (Operation ());
1512 val debug_dispatcher_program_pointer = Output (UInt (8 .W ));
1613 });
1714
1815 val memory = Module (new Memory ());
1916 val dispatcher = Module (new Dispatcher ());
17+ val thread = Module (new Thread ());
2018
2119 memory.io.readPorts(0 ).enable := dispatcher.io.read_requested;
2220 memory.io.readPorts(0 ).address := dispatcher.io.read_program_pointer;
@@ -25,8 +23,8 @@ class Core extends Module {
2523 memory.io.writePorts(0 ).address := io.debug_memory_write_address;
2624 memory.io.writePorts(0 ).data := io.debug_memory_write_data;
2725
28- dispatcher.io.thread_requesting_opcode := io.debug_dispatcher_thread_requesting_opcode ;
29- dispatcher.io.thread_program_pointer := io.debug_dispatcher_thread_program_pointer ;
26+ dispatcher.io.thread_requesting_opcode := thread. io.idle ;
27+ dispatcher.io.thread_program_pointer := thread. io.program_pointer ;
3028
3129 val read_ready_delayed = RegNext (dispatcher.io.read_requested, false .B );
3230 dispatcher.io.read_ready := read_ready_delayed;
@@ -42,10 +40,9 @@ class Core extends Module {
4240 io.debug_dispatcher_opcode := dispatcher.io.opcode;
4341 io.debug_dispatcher_program_pointer := dispatcher.io.program_pointer;
4442
45- val thread = Module (new Thread ());
4643 thread.io.dispatcher_opcode_loaded := dispatcher.io.opcode_loaded;
4744 thread.io.dispatcher_program_pointer := dispatcher.io.program_pointer;
4845 thread.io.operation := dispatcher.io.opcode;
49- thread.io.immediate_a := 0 .U (8 .W );
50- thread.io.immediate_b := 0 .U (8 .W );
46+ thread.io.immediate_a := 2 .U (8 .W );
47+ thread.io.immediate_b := 3 .U (8 .W );
5148}
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