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Commit 93790ab

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Update before operation changes
1 parent a3f9442 commit 93790ab

2 files changed

Lines changed: 2 additions & 3 deletions

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src/main/scala/main/Thread.scala

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ class Thread extends Module {
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})
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val end_of_program = RegInit(false.B);
22-
val idle = RegInit(true.B);
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val register_a = RegInit(0.U(16.W));
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val register_b = RegInit(0.U(16.W));
@@ -56,7 +55,7 @@ class Thread extends Module {
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io.program_pointer := program_counter.io.program_counter;
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io.end_of_program := end_of_program;
59-
io.idle := idle;
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io.idle := false.B;
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when(
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io.dispatcher_opcode_loaded && io.dispatcher_program_pointer === program_counter.io.program_counter
@@ -151,7 +150,7 @@ class Thread extends Module {
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}
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when(
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executing_load_write || io.operation === Operation.Write || io.operation === Operation.Load
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io.operation === Operation.Write || io.operation === Operation.Load && !executing_load_write
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) {
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io.idle := false.B;
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executing_load_write := true.B;

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