Implement register codes

Author: outercloudstudio

README.md

@@ -29,6 +29,7 @@ A single thread contains a program counter, ALU, LSU, and registers. Thread take
 2. a, b, and c register
 ### Instruction Set
 The instruction set is 24 bits wide. 8 for opcode and 16 additional bits for immediate. The first 5 opcode bits specify instruction. The next 3 specify target or source / destination registers if an instruction uses it.
+#### Opcodes
 - move
 	`00001` + target --> moves immediate into register
 	`00010` + src/dst --> moves value in register to register
@@ -68,7 +69,14 @@ The instruction set is 24 bits wide. 8 for opcode and 16 additional bits for imm
 	`10101` --> signals that the thread has finished execution
 - store
 	`10110` + src/dst --> takes address from src register and stores the value in dst register into memory
-	
+#### Register Codes
+`000` --> A --> B
+`001` --> A --> C
+`010` --> B --> A
+`011` --> B --> C
+`100` --> C --> A
+`101` --> C --> B
+
 Potentially we may need more instructions but I can't think of any more that we need right now?
 # How To Run
 `sbt run test`

src/main/scala/main/Core.scala

@@ -34,7 +34,7 @@ class Core extends Module {
 
   val read_ready_delayed = RegNext(dispatcher.io.read_requested, false.B);
   dispatcher.io.read_ready := read_ready_delayed;
-  dispatcher.io.read_opcode := Operation.safe(memory.io.readPorts(0).data(6, 3))._1;
+  dispatcher.io.read_opcode := memory.io.readPorts(0).data(7, 0);
   dispatcher.io.read_immediate_l := memory.io.readPorts(1).data(7, 0);
   dispatcher.io.read_immediate_u := memory.io.readPorts(2).data(7, 0);
 
@@ -57,6 +57,8 @@ class Core extends Module {
   thread.io.dispatcher_opcode_loaded := dispatcher.io.opcode_loaded;
   thread.io.dispatcher_program_pointer := dispatcher.io.program_pointer;
   thread.io.operation := dispatcher.io.opcode;
+  thread.io.src_register := dispatcher.io.src_register;
+  thread.io.dst_register := dispatcher.io.dst_register;
   thread.io.immediate_a := 2.U(8.W);
   thread.io.immediate_b := 3.U(8.W);
 

src/main/scala/main/Dispatcher.scala

@@ -11,12 +11,14 @@ class Dispatcher extends Module {
     val read_requested = Output(UInt(8.W));
     val read_program_pointer = Output(UInt(8.W));
     val read_ready = Input(Bool());
-    val read_opcode = Input(Operation());
+    val read_opcode = Input(UInt(8.W));
     val read_immediate_l = Input(UInt(8.W));
     val read_immediate_u = Input(UInt(8.W));
 
     val opcode_loaded = Output(Bool());
     val opcode = Output(Operation());
+    val src_register = Output(Register());
+    val dst_register = Output(Register());
     val program_pointer = Output(UInt(8.W));
   });
 
@@ -29,12 +31,17 @@ class Dispatcher extends Module {
   io.opcode_loaded := opcode_loaded;
   val opcode = RegInit(Operation.NoOp);
   io.opcode := opcode;
+  val src_register = RegInit(Register.A);
+  io.src_register := src_register;
+  val dst_register = RegInit(Register.B);
+  io.dst_register := dst_register;
   val program_pointer = RegInit(0.U(8.W));
   io.program_pointer := program_pointer;
 
   when(io.thread_requesting_opcode) {
     printf(p"\t[Dispatcher]=====");
     printf(p"\n\t\tMarked read requested!\n\n");
+
     read_program_pointer := io.thread_program_pointer;
     read_requested := true.B;
   }
@@ -43,10 +50,46 @@ class Dispatcher extends Module {
     printf(p"\t[Dispatcher]=====");
     printf(p"\n\t\tRead Complete ${io.read_opcode}");
     printf(p"\n\t\tImmediate Lower ${io.read_immediate_l}");
-    printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}\n\n");
-    opcode := io.read_opcode;
+    printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}");
+
+    opcode := Operation.safe(io.read_opcode(6, 3))._1;
+    
+    val registers_code = io.read_opcode(2, 0);
+
+    when(registers_code === 0.U) {
+      src_register := Register.A;
+      dst_register := Register.B;
+    }
+
+    when(registers_code === 1.U) {
+      src_register := Register.A;
+      dst_register := Register.C;
+    }
+
+    when(registers_code === 2.U) {
+      src_register := Register.B;
+      dst_register := Register.A;
+    }
+
+    when(registers_code === 3.U) {
+      src_register := Register.B;
+      dst_register := Register.C;
+    }
+
+    when(registers_code === 4.U) {
+      src_register := Register.C;
+      dst_register := Register.A;
+    }
+
+    when(registers_code === 5.U) {
+      src_register := Register.C;
+      dst_register := Register.B;
+    }
+
     opcode_loaded := true.B;
+    
     program_pointer := io.read_program_pointer;
+    
     read_requested := false.B;
   }
 }

src/main/scala/main/Register.scala

@@ -0,0 +1,7 @@
+import chisel3._
+import chisel3.util._
+import _root_.circt.stage.ChiselStage
+
+object Register extends ChiselEnum {
+  val A, B, C = Value
+}

src/main/scala/main/Thread.scala

@@ -8,6 +8,8 @@ class Thread extends Module {
     val dispatcher_program_pointer = Input(UInt(8.W));
 
     val operation = Input(Operation());
+    val src_register = Input(Register());
+    val dst_register = Input(Register());
     val immediate_a = Input(UInt(8.W));
     val immediate_b = Input(UInt(8.W));
 
@@ -52,9 +54,33 @@ class Thread extends Module {
     when(io.operation === Operation.Add || io.operation === Operation.Sub || io.operation === Operation.Mul || io.operation === Operation.Div) {
       alu.io.execute := true.B;
       alu.io.operation := io.operation;
-      alu.io.rs := register_a;
-      alu.io.rt := register_b;
-      register_a := alu.io.output
+
+      when(io.src_register === Register.A) {
+        alu.io.rs := register_a;
+      }
+
+      when(io.src_register === Register.B) {
+        alu.io.rs := register_b;
+      }
+
+      when(io.src_register === Register.C) {
+        alu.io.rs := register_c;
+      }
+
+      when(io.dst_register === Register.A) {
+        alu.io.rt := register_a;
+        register_a := alu.io.output
+      }
+
+      when(io.dst_register === Register.B) {
+        alu.io.rt := register_b;
+        register_b := alu.io.output
+      }
+
+      when(io.dst_register === Register.C) {
+        alu.io.rt := register_c;
+        register_c := alu.io.output
+      }
 
       program_counter.io.update := true.B;
       program_counter.io.branch := false.B;