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Add LSU reading data
1 parent b923528 commit b1f5075

3 files changed

Lines changed: 92 additions & 2 deletions

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src/main/scala/main/Lsu.scala

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import chisel3._
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import chisel3.util._
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import _root_.circt.stage.ChiselStage
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object LsuState extends ChiselEnum {
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val Idle, Requesting = Value
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}
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class Lsu extends Module {
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val io = IO(new Bundle {
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val read = Input(Bool());
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// val write = Input(Bool());
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val address = Input(UInt(8.W));
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// val value = Input(UInt(8.W));
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val read_requested = Output(Bool());
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val read_address = Output(UInt(8.W));
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val read_ready = Input(Bool());
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val read_data = Input(UInt(8.W));
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// val write_ready = Input(Bool());
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// val write_data = Output(UInt(8.W));
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// val write_valid = Output(Bool());
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// val write_address = Output(UInt(8.W));
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val state = Output(LsuState());
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val output = Output(UInt(8.W));
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})
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val state = RegInit(LsuState.Idle);
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io.state := state;
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val output = RegInit(0.U(8.W));
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io.output := output;
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val read_requested = RegInit(false.B);
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io.read_requested := read_requested;
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val read_address = RegInit(false.B);
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io.read_address := read_address;
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when(io.read) {
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switch(io.state) {
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is(LsuState.Idle) {
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state := LsuState.Requesting;
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read_requested := true.B;
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read_address := io.address;
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}
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is(LsuState.Requesting) {
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when(io.read_ready) {
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state := LsuState.Idle;
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read_requested := false.B;
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output := io.read_data;
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}
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}
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}
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}
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}

src/main/scala/main/Main.scala

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@@ -3,6 +3,6 @@ import chisel3.util._
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import _root_.circt.stage.ChiselStage
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object Main extends App {
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println("Generating Alu")
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emitVerilog(new Alu(), Array("--target-dir", "generated"))
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emitVerilog(new Alu(), Array("--target-dir", "generated"));
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emitVerilog(new Lsu(), Array("--target-dir", "generated"));
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}

src/test/scala/main/LsuTest.scala

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import chisel3._
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import chiseltest._
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import org.scalatest.flatspec.AnyFlatSpec
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class LsuTest extends AnyFlatSpec with ChiselScalatestTester {
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"Lsu" should "work" in {
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test(new Lsu) { dut =>
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dut.io.read.poke(true.B);
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dut.io.address.poke(1.U);
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dut.clock.step(1);
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dut.io.state.expect(LsuState.Requesting);
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dut.io.read_requested.expect(true.B);
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dut.io.read_address.expect(1.U);
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dut.clock.step(1);
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dut.clock.step(1);
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dut.io.state.expect(LsuState.Requesting);
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dut.io.read_ready.poke(true.B);
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dut.io.read_data.poke(5.U);
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dut.clock.step(1);
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dut.io.state.expect(LsuState.Idle);
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dut.io.output.expect(5.U);
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}
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}
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}

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