Skip to content

Commit b255b44

Browse files
Add LSU Writing
1 parent b1f5075 commit b255b44

3 files changed

Lines changed: 61 additions & 8 deletions

File tree

src/main/scala/main/Lsu.scala

Lines changed: 33 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,20 +9,20 @@ object LsuState extends ChiselEnum {
99
class Lsu extends Module {
1010
val io = IO(new Bundle {
1111
val read = Input(Bool());
12-
// val write = Input(Bool());
12+
val write = Input(Bool());
1313

1414
val address = Input(UInt(8.W));
15-
// val value = Input(UInt(8.W));
15+
val data = Input(UInt(8.W));
1616

1717
val read_requested = Output(Bool());
1818
val read_address = Output(UInt(8.W));
1919
val read_ready = Input(Bool());
2020
val read_data = Input(UInt(8.W));
2121

22-
// val write_ready = Input(Bool());
23-
// val write_data = Output(UInt(8.W));
24-
// val write_valid = Output(Bool());
25-
// val write_address = Output(UInt(8.W));
22+
val write_requested = Output(Bool());
23+
val write_data = Output(UInt(8.W));
24+
val write_address = Output(UInt(8.W));
25+
val write_ready = Input(Bool());
2626

2727
val state = Output(LsuState());
2828
val output = Output(UInt(8.W));
@@ -40,6 +40,15 @@ class Lsu extends Module {
4040
val read_address = RegInit(false.B);
4141
io.read_address := read_address;
4242

43+
val write_requested = RegInit(false.B);
44+
io.write_requested := write_requested;
45+
46+
val write_address = RegInit(0.U(8.W));
47+
io.write_address := write_address;
48+
49+
val write_data = RegInit(0.U(8.W));
50+
io.write_data := write_data;
51+
4352
when(io.read) {
4453
switch(io.state) {
4554
is(LsuState.Idle) {
@@ -57,4 +66,22 @@ class Lsu extends Module {
5766
}
5867
}
5968
}
69+
70+
when(io.write) {
71+
switch(io.state) {
72+
is(LsuState.Idle) {
73+
state := LsuState.Requesting;
74+
write_requested := true.B;
75+
write_address := io.address;
76+
write_data := io.data
77+
}
78+
79+
is(LsuState.Requesting) {
80+
when(io.write_ready) {
81+
state := LsuState.Idle;
82+
write_requested := false.B;
83+
}
84+
}
85+
}
86+
}
6087
}

src/test/scala/main/AluTest.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ import chiseltest._
33
import org.scalatest.flatspec.AnyFlatSpec
44

55
class AluTest extends AnyFlatSpec with ChiselScalatestTester {
6-
"Alu" should "work" in {
6+
"Alu Add" should "work" in {
77
test(new Alu) { dut =>
88
dut.io.enable.poke(true.B);
99
dut.io.operation.poke(AluOperation.Add);

src/test/scala/main/LsuTest.scala

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ import chiseltest._
33
import org.scalatest.flatspec.AnyFlatSpec
44

55
class LsuTest extends AnyFlatSpec with ChiselScalatestTester {
6-
"Lsu" should "work" in {
6+
"Lsu Read" should "work" in {
77
test(new Lsu) { dut =>
88
dut.io.read.poke(true.B);
99
dut.io.address.poke(1.U);
@@ -27,4 +27,30 @@ class LsuTest extends AnyFlatSpec with ChiselScalatestTester {
2727
dut.io.output.expect(5.U);
2828
}
2929
}
30+
31+
"Lsu Write" should "work" in {
32+
test(new Lsu) { dut =>
33+
dut.io.write.poke(true.B);
34+
dut.io.address.poke(1.U);
35+
dut.io.data.poke(2.U);
36+
37+
dut.clock.step(1);
38+
39+
dut.io.state.expect(LsuState.Requesting);
40+
dut.io.write_requested.expect(true.B);
41+
dut.io.write_address.expect(1.U);
42+
dut.io.write_data.expect(2.U);
43+
44+
dut.clock.step(1);
45+
dut.clock.step(1);
46+
47+
dut.io.state.expect(LsuState.Requesting);
48+
49+
dut.io.write_ready.poke(true.B);
50+
51+
dut.clock.step(1);
52+
53+
dut.io.state.expect(LsuState.Idle);
54+
}
55+
}
3056
}

0 commit comments

Comments
 (0)