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Implement dispatcher
1 parent 02e406b commit d8c1611

3 files changed

Lines changed: 47 additions & 6 deletions

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src/main/scala/main/Dispatcher.scala

Lines changed: 29 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,36 @@ import _root_.circt.stage.ChiselStage
44

55
class Dispatcher extends Module {
66
val io = IO(new Bundle {
7-
val read_requested = Output(Bool());
8-
val read_address = Output(UInt(8.W));
7+
val thread_requesting_opcode = Input(Bool());
8+
val thread_program_pointer = Input(UInt(8.W));
9+
10+
val read_requested = Output(UInt(8.W));
11+
val read_program_pointer = Output(UInt(8.W));
912
val read_ready = Input(Bool());
10-
val read_data = Input(UInt(8.W));
13+
val read_opcode = Input(Operation());
14+
15+
val opcode = Output(Operation());
16+
val program_pointer = Output(UInt(8.W));
1117
});
1218

13-
val memory = SRAM(1024, UInt(8.W), 2, 2);
19+
val read_requested = RegInit(0.U(8.W));
20+
io.read_requested := read_requested;
21+
val read_program_pointer = RegInit(0.U(8.W));
22+
io.read_program_pointer := read_program_pointer;
23+
24+
val opcode = RegInit(Operation.NoOp);
25+
io.opcode := opcode;
26+
val program_pointer = RegInit(0.U(8.W));
27+
io.program_pointer := program_pointer;
28+
29+
when(io.thread_requesting_opcode) {
30+
read_program_pointer := io.thread_program_pointer;
31+
read_requested := true.B;
32+
}
33+
34+
when(io.read_ready) {
35+
opcode := io.read_opcode;
36+
program_pointer := io.read_program_pointer;
37+
read_requested := false.B;
38+
}
1439
}

src/main/scala/main/Memory.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ import chisel3.util._
33
import _root_.circt.stage.ChiselStage
44

55
class Memory extends Module {
6-
val io = IO(new SRAMInterface(1024, UInt(8.W), 1, 1));
6+
val io = IO(new SRAMInterface(1024, UInt(8.W), 1, 1, 0));
77

8-
val memory = SRAM(1024, UInt(8.W), 1, 1);
8+
val memory = SRAM(1024, UInt(8.W), 1, 1, 0);
99
}

src/test/scala/main/DispatcherTest.scala

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,23 @@ import org.scalatest.flatspec.AnyFlatSpec
55
class DispatcherTest extends AnyFlatSpec with ChiselScalatestTester {
66
"Dispatcher" should "work" in {
77
test(new Dispatcher) { dut =>
8+
dut.io.thread_requesting_opcode.poke(true.B);
9+
dut.io.thread_program_pointer.poke(1.U(8.W));
10+
11+
dut.clock.step(1);
12+
13+
dut.io.read_requested.expect(true.B);
14+
dut.io.read_program_pointer.expect(1.U(8.W));
815

16+
dut.clock.step(1);
17+
18+
dut.io.read_ready.poke(true.B);
19+
dut.io.read_opcode.poke(Operation.Add);
20+
21+
dut.clock.step(1);
22+
23+
dut.io.opcode.expect(Operation.Add);
24+
dut.io.program_pointer.expect(1.U(8.W));
925
}
1026
}
1127
}

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