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Do some cleanup on the ALU
1 parent 840aeaf commit e979cf2

3 files changed

Lines changed: 2 additions & 10 deletions

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src/main/scala/main/Alu.scala

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -30,17 +30,9 @@ class Alu extends Module {
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io.output := io.rs + io.rt;
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}
3232

33-
is(Operation.Sub) {
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io.output := io.rs - io.rt;
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}
36-
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is(Operation.Mul) {
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io.output := io.rs * io.rt;
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}
40-
41-
is(Operation.Div) {
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io.output := io.rs / io.rt;
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}
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}
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}
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}

src/main/scala/main/Operation.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,5 +3,5 @@ import chisel3.util._
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import _root_.circt.stage.ChiselStage
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object Operation extends ChiselEnum {
6-
val NoOp, MoveImmediate, MoveRegister, Load, Add, Sub, Mul, Div, JumpE, JumpNE, Compare, End, Write = Value
6+
val NoOp, MoveImmediate, MoveRegister, Load, Add, Mul, Compare, JumpE, JumpNE, End, Write = Value
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}

src/main/scala/main/Thread.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ class Thread extends Module {
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io.idle := idle;
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when(io.dispatcher_opcode_loaded && io.dispatcher_program_pointer === program_counter.io.program_counter) {
53-
when(io.operation === Operation.Add || io.operation === Operation.Sub || io.operation === Operation.Mul || io.operation === Operation.Div) {
53+
when(io.operation === Operation.Add || io.operation === Operation.Mul || io.operation === Operation.Compare) {
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alu.io.execute := true.B;
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alu.io.operation := io.operation;
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