|
54 | 54 | #endif |
55 | 55 | #endif |
56 | 56 |
|
| 57 | +#if defined(__loongarch64) |
| 58 | +#define CPUINFO_ARCH_LOONGARCH64 1 |
| 59 | +#endif |
| 60 | + |
57 | 61 | /* Define other architecture-specific macros as 0 */ |
58 | 62 |
|
59 | 63 | #ifndef CPUINFO_ARCH_X86 |
|
96 | 100 | #define CPUINFO_ARCH_RISCV64 0 |
97 | 101 | #endif |
98 | 102 |
|
| 103 | +#ifndef CPUINFO_ARCH_LOONGARCH64 |
| 104 | +#define CPUINFO_ARCH_LOONGARCH64 0 |
| 105 | +#endif |
| 106 | + |
99 | 107 | #if CPUINFO_ARCH_X86 && defined(_MSC_VER) |
100 | 108 | #define CPUINFO_ABI __cdecl |
101 | 109 | #elif CPUINFO_ARCH_X86 && defined(__GNUC__) |
@@ -304,6 +312,10 @@ enum cpuinfo_vendor { |
304 | 312 | * in 1997. |
305 | 313 | */ |
306 | 314 | cpuinfo_vendor_dec = 57, |
| 315 | + /** |
| 316 | + * Loongson. Vendor of LOONGARCH processor microarchitecture. |
| 317 | + */ |
| 318 | + cpuinfo_vendor_loongson = 58, |
307 | 319 | }; |
308 | 320 |
|
309 | 321 | /** |
@@ -601,6 +613,9 @@ enum cpuinfo_uarch { |
601 | 613 |
|
602 | 614 | /** HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors). */ |
603 | 615 | cpuinfo_uarch_taishan_v110 = 0x00C00100, |
| 616 | + |
| 617 | + /** Loongson LA4 64 (Loongarch3 series processors). */ |
| 618 | + cpuinfo_uarch_LA464 = 0x00D00100, |
604 | 619 | }; |
605 | 620 |
|
606 | 621 | struct cpuinfo_processor { |
@@ -635,6 +650,10 @@ struct cpuinfo_processor { |
635 | 650 | #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 |
636 | 651 | /** APIC ID (unique x86-specific ID of the logical processor) */ |
637 | 652 | uint32_t apic_id; |
| 653 | +#endif |
| 654 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 655 | + /** CPUCFG ID (unique loongarch-specific ID of the logical processor) */ |
| 656 | + uint32_t cpucfg_id; |
638 | 657 | #endif |
639 | 658 | struct { |
640 | 659 | /** Level 1 instruction cache */ |
@@ -671,6 +690,9 @@ struct cpuinfo_core { |
671 | 690 | #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
672 | 691 | /** Value of Main ID Register (MIDR) for this core */ |
673 | 692 | uint32_t midr; |
| 693 | +#elif CPUINFO_ARCH_LOONGARCH64 |
| 694 | + /** Value of CPUCFG for this core */ |
| 695 | + uint32_t cpucfg; |
674 | 696 | #endif |
675 | 697 | /** Clock rate (non-Turbo) of the core, in Hz */ |
676 | 698 | uint64_t frequency; |
@@ -699,6 +721,9 @@ struct cpuinfo_cluster { |
699 | 721 | #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
700 | 722 | /** Value of Main ID Register (MIDR) of the cores in the cluster */ |
701 | 723 | uint32_t midr; |
| 724 | +#elif CPUINFO_ARCH_LOONGARCH64 |
| 725 | + /** Value of CPUCFG for this cores in the cluster */ |
| 726 | + uint32_t cpucfg; |
702 | 727 | #endif |
703 | 728 | /** Clock rate (non-Turbo) of the cores in the cluster, in Hz */ |
704 | 729 | uint64_t frequency; |
@@ -732,6 +757,9 @@ struct cpuinfo_uarch_info { |
732 | 757 | #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 |
733 | 758 | /** Value of Main ID Register (MIDR) for the microarchitecture */ |
734 | 759 | uint32_t midr; |
| 760 | +#elif CPUINFO_ARCH_LOONGARCH64 |
| 761 | + /** Value of CPUCFG for the microarchitecture */ |
| 762 | + uint32_t cpucfg; |
735 | 763 | #endif |
736 | 764 | /** Number of logical processors with the microarchitecture */ |
737 | 765 | uint32_t processor_count; |
@@ -2227,6 +2255,132 @@ static inline bool cpuinfo_has_riscv_v(void) { |
2227 | 2255 | #endif |
2228 | 2256 | } |
2229 | 2257 |
|
| 2258 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2259 | +/* This structure is not a part of stable API. Use cpuinfo_has_loongarch_* functions instead. */ |
| 2260 | +struct cpuinfo_loongarch_isa { |
| 2261 | + bool cpucfg; |
| 2262 | + bool lam; |
| 2263 | + bool ual; |
| 2264 | + bool fpu; |
| 2265 | + bool lsx; |
| 2266 | + bool lasx; |
| 2267 | + |
| 2268 | + bool crc32; |
| 2269 | + bool complex; |
| 2270 | + bool crypto; |
| 2271 | + bool lvz; |
| 2272 | + bool lbt_x86; |
| 2273 | + bool lbt_arm; |
| 2274 | + bool lbt_mips; |
| 2275 | +}; |
| 2276 | + |
| 2277 | +extern struct cpuinfo_loongarch_isa cpuinfo_isa; |
| 2278 | +#endif |
| 2279 | + |
| 2280 | +static inline bool cpuinfo_has_loongarch_cpucfg(void) { |
| 2281 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2282 | + return cpuinfo_isa.cpucfg; |
| 2283 | +#else |
| 2284 | + return false; |
| 2285 | +#endif |
| 2286 | +} |
| 2287 | + |
| 2288 | +static inline bool cpuinfo_has_loongarch_lam(void) { |
| 2289 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2290 | + return cpuinfo_isa.lam; |
| 2291 | +#else |
| 2292 | + return false; |
| 2293 | +#endif |
| 2294 | +} |
| 2295 | + |
| 2296 | +static inline bool cpuinfo_has_loongarch_ual(void) { |
| 2297 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2298 | + return cpuinfo_isa.ual; |
| 2299 | +#else |
| 2300 | + return false; |
| 2301 | +#endif |
| 2302 | +} |
| 2303 | + |
| 2304 | +static inline bool cpuinfo_has_loongarch_fpu(void) { |
| 2305 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2306 | + return cpuinfo_isa.fpu; |
| 2307 | +#else |
| 2308 | + return false; |
| 2309 | +#endif |
| 2310 | +} |
| 2311 | + |
| 2312 | +static inline bool cpuinfo_has_loongarch_lsx(void) { |
| 2313 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2314 | + return cpuinfo_isa.lsx; |
| 2315 | +#else |
| 2316 | + return false; |
| 2317 | +#endif |
| 2318 | +} |
| 2319 | + |
| 2320 | +static inline bool cpuinfo_has_loongarch_lasx(void) { |
| 2321 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2322 | + return cpuinfo_isa.lasx; |
| 2323 | +#else |
| 2324 | + return false; |
| 2325 | +#endif |
| 2326 | +} |
| 2327 | + |
| 2328 | +static inline bool cpuinfo_has_loongarch_crc32(void) { |
| 2329 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2330 | + return cpuinfo_isa.crc32; |
| 2331 | +#else |
| 2332 | + return false; |
| 2333 | +#endif |
| 2334 | +} |
| 2335 | + |
| 2336 | +static inline bool cpuinfo_has_loongarch_complex(void) { |
| 2337 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2338 | + return cpuinfo_isa.complex; |
| 2339 | +#else |
| 2340 | + return false; |
| 2341 | +#endif |
| 2342 | +} |
| 2343 | + |
| 2344 | +static inline bool cpuinfo_has_loongarch_crypto(void) { |
| 2345 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2346 | + return cpuinfo_isa.crypto; |
| 2347 | +#else |
| 2348 | + return false; |
| 2349 | +#endif |
| 2350 | +} |
| 2351 | + |
| 2352 | +static inline bool cpuinfo_has_loongarch_lvz(void) { |
| 2353 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2354 | + return cpuinfo_isa.lvz; |
| 2355 | +#else |
| 2356 | + return false; |
| 2357 | +#endif |
| 2358 | +} |
| 2359 | + |
| 2360 | +static inline bool cpuinfo_has_loongarch_lbt_x86(void) { |
| 2361 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2362 | + return cpuinfo_isa.lbt_x86; |
| 2363 | +#else |
| 2364 | + return false; |
| 2365 | +#endif |
| 2366 | +} |
| 2367 | + |
| 2368 | +static inline bool cpuinfo_has_loongarch_lbt_arm(void) { |
| 2369 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2370 | + return cpuinfo_isa.lbt_arm; |
| 2371 | +#else |
| 2372 | + return false; |
| 2373 | +#endif |
| 2374 | +} |
| 2375 | + |
| 2376 | +static inline bool cpuinfo_has_loongarch_lbt_mips(void) { |
| 2377 | +#if CPUINFO_ARCH_LOONGARCH64 |
| 2378 | + return cpuinfo_isa.lbt_mips; |
| 2379 | +#else |
| 2380 | + return false; |
| 2381 | +#endif |
| 2382 | +} |
| 2383 | + |
2230 | 2384 | const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void); |
2231 | 2385 | const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_cores(void); |
2232 | 2386 | const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_clusters(void); |
|
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