@@ -126,7 +126,7 @@ static uint64_t esp32_rtc_cntl_read(void *opaque, hwaddr addr, unsigned int size
126126 break ;
127127 }
128128 if (DEBUG )
129- printf ("RTC_CNTL Read %lx %lx \n" ,addr ,r );
129+ printf ("RTC_CNTL Read %x %x \n" ,( uint32_t ) addr ,( uint32_t ) r );
130130 return r ;
131131}
132132
@@ -135,7 +135,7 @@ static void esp32_rtc_cntl_write(void *opaque, hwaddr addr, uint64_t value,
135135{
136136 Esp32RtcCntlState * s = ESP32_RTC_CNTL (opaque );
137137 if (DEBUG )
138- printf ("RTC_CNTL Write %lx %lx \n" ,addr ,value );
138+ printf ("RTC_CNTL Write %x %x \n" ,( uint32_t ) addr , ( uint32_t ) value );
139139 switch (addr ) {
140140 case A_RTC_CNTL_OPTIONS0 :
141141 if (value & R_RTC_CNTL_OPTIONS0_SW_SYS_RESET_MASK ) {
@@ -183,7 +183,7 @@ static void esp32_rtc_cntl_write(void *opaque, hwaddr addr, uint64_t value,
183183 sleep_time - s -> time_reg , NANOSECONDS_PER_SECOND ,
184184 s -> rtc_slowclk_freq );
185185 if (DEBUG )
186- printf ("Sleep %ld , %ld , %d, %ld \n" ,s -> time_reg , sleep_time , timer_en , sleep_ns );
186+ printf ("Sleep %d , %d , %d, %d \n" ,( uint32_t ) s -> time_reg , ( uint32_t ) sleep_time , timer_en , ( uint32_t ) sleep_ns );
187187 if (timer_en )
188188 timer_mod (& s -> sleep_timer , qemu_clock_get_ns (QEMU_CLOCK_REALTIME )+ sleep_ns );
189189 s -> low_power_state_reg = FIELD_DP32 (s -> low_power_state_reg ,RTC_CNTL_LOW_POWER_ST_REG , RTC_RDY_FOR_WAKEUP ,1 );
@@ -232,7 +232,7 @@ static void esp32_rtc_cntl_write(void *opaque, hwaddr addr, uint64_t value,
232232 break ;
233233 case A_RTC_CNTL_EXT_WAKEUP_CONF :
234234 if (DEBUG )
235- printf ("wakeup_conf %lx \n" ,value );
235+ printf ("wakeup_conf %x \n" ,( uint32_t ) value );
236236 s -> wakeup_conf = value ;
237237 break ;
238238 case A_RTC_MEM_CONF :
0 commit comments