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Merge pull request #19 from MicrochipTech/dev
Merge dev to main after v2022.2.1 release
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‎Libero/README.txt‎

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Each of the Training directories contains a Libero subdirectory which can be
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used to regenerate the training for new versions of Libero.
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Each of the Libero subdirectories contains the following:
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1. readme.txt - this file lists the commands to regenerate the training project
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using the tcl flow.
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2. softconsole - this folder has the original Softconsole project. You can use
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this in case you want to regenerate the hex file to be used in the
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Libero project.
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3. src - this folder has all the source files used to recreate the Libero project.
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4. libero_flow.tcl - this is the file that needs to be sourced to the Libero
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executable in script mode. You can also run this file in the IDE by
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selecting <Project><Execute Script>
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Note: While running libero_flow.tcl, if you see a failure in configuring a
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particular core because it is no longer supported in that particular Libero
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release, you can edit the top of libero_flow.tcl to update the version of
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that particular core with the latest version.

‎Libero/libero_generate_job.tcl‎

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# to run:
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# libero SCRIPT:libero_generate_job.tcl SCRIPT_ARGS:"<libero_prjx_file> <job_file_name>"
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#
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# store arguments in parameters
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set project [lindex $argv 0]
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set job_file [lindex $argv 1]
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open_project -file $project
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# Workaround to fix Linux Synthesis issue with Libero project. TODO: update original Libero project
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# Synthesis is failing with missing mux_3_to_1_8bit module. To avaoid this, added the below code to re-import the corresponding hdl file and to regenerate the top component
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import_files \
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-convert_EDN_to_HDL 0 \
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-library {work} \
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-hdl_source {./LegUp_Training1_Libero/hdl/mux_3_to_1_8bit.v}
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save_project
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generate_component -component_name {LegUp_Image_Filters} -recursive 1
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generate_component -component_name {VIDEO_KIT_TOP} -recursive 1
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build_design_hierarchy
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# we purposely don't change any synthesis or P&R settings to reproduce what the user will do
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# when they download the Libero project
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run_tool -name {SYNTHESIZE}
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run_tool -name {PLACEROUTE}
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run_tool -name {VERIFYTIMING}
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# regenerate the .job file
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export_prog_job \
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-job_file_name $job_file \
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-export_dir {.} \
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-bitstream_file_type {TRUSTED_FACILITY} \
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-bitstream_file_components {FABRIC_SNVM} \
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-zeroization_likenew_action 0 \
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-zeroization_unrecoverable_action 0 \
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-program_design 1 \
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-program_spi_flash 0 \
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-include_plaintext_passkey 0 \
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-design_bitstream_format {PPD} \
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-prog_optional_procedures {} \
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-skip_recommended_procedures {} \
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-sanitize_snvm 0

‎Libero/libero_update_hls_core.tcl‎

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# to run:
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# libero SCRIPT:libero_update_hls_core.tcl SCRIPT_ARGS:"<libero_prjx_file> <top_component> <hdl_core_name> <verilog_file> <create_hdl_plus> <current_sd_name> <instance_update>"
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#
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# store arguments in parameters
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set project [lindex $argv 0]
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set top_component [lindex $argv 1]
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set hdl_core_name [lindex $argv 2]
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set verilog_file [lindex $argv 3]
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set create_hdl_plus [lindex $argv 4]
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set current_sd_name [lindex $argv 5]
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set instance_update [lindex $argv 6]
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# added the below argument to take into account the name change of hls module from legup to smarthls
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set new_hdl_core_name [string map {legup smarthls} $hdl_core_name]
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open_project -file $project
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remove_hdl_core -hdl_core_name $hdl_core_name
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delete_files -file $verilog_file -from_disk
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# re-create the SmartHLS core
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source $create_hdl_plus
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open_smartdesign -sd_name $current_sd_name
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sd_replace_component -sd_name $current_sd_name -instance_name $instance_update -new_component_name $new_hdl_core_name -replace_all_instances 1
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save_smartdesign -sd_name $current_sd_name
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generate_component -component_name $current_sd_name -recursive 1
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generate_component -component_name $top_component -recursive 1
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build_design_hierarchy
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save_project
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close_project

‎Training1/Libero/libero_flow.tcl‎

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#Libero project creation
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new_project -location {./Libero_training1} -name {Libero_training1} -project_description {} -block_mode 0 -hdl Verilog -family {PolarFire} -die {MPF300TS} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {IND} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESERVEMIGRATIONPINS:1} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:IND} -adv_options {UNUSED_MSS_IO_RESISTOR_PULL:None} -adv_options {VCCI_1.2_VOLTR:IND} -adv_options {VCCI_1.5_VOLTR:IND} -adv_options {VCCI_1.8_VOLTR:IND} -adv_options {VCCI_2.5_VOLTR:IND} -adv_options {VCCI_3.3_VOLTR:IND} -adv_options {VOLTR:IND}
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set PF_CCC_version 2.2.214
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set Display_Controller_version 3.1.2
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set HDMI_RX_version 4.2.0
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set HDMI_TX_version 1.0.2
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set PF_TX_PLL_version 2.0.300
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set PF_XCVR_ERM_version 3.1.200
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set PF_XCVR_REF_CLK_version 1.0.103
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set CORERESET_PF_version 2.2.107
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set CORERXIODBITALIGN_version 2.1.104
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set PF_IOD_GENERIC_RX_version 2.1.109
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set PF_DDR4_version 2.5.108
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set PF_SRAM_AHBL_AXI_version 1.2.108
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set mipicsi2rxdecoderPF_version 2.2.5
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set COREAHBTOAPB3_version 3.1.100
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set COREI2C_version 7.2.101
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set CoreAPB3_version 4.1.100
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set CoreGPIO_version 3.2.102
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set COREJTAGDEBUG_version 3.1.100
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set CoreAHBLite_version 5.4.102
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set PF_INIT_MONITOR_version 2.0.304
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set MIV_RV32IMA_L1_AHB_version 2.3.100
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set COREUART_version 5.6.102
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set Bayer_Interpolation_version 3.0.2
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set Image_Enhancement_version 3.0.0
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#Download all the required cores to the vault
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download_core -vlnv "Actel:SgCore:PF_CCC:${PF_CCC_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Microsemi:SolutionCore:Display_Controller:${Display_Controller_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Microsemi:SolutionCore:HDMI_RX:${HDMI_RX_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Microsemi:SolutionCore:HDMI_TX:${HDMI_TX_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:SgCore:PF_TX_PLL:${PF_TX_PLL_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Actel:SystemBuilder:PF_XCVR_ERM:${PF_XCVR_ERM_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Actel:SgCore:PF_XCVR_REF_CLK:${PF_XCVR_REF_CLK_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Actel:DirectCore:CORERESET_PF:${CORERESET_PF_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:CORERXIODBITALIGN:${CORERXIODBITALIGN_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:SystemBuilder:PF_IOD_GENERIC_RX:${PF_IOD_GENERIC_RX_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Actel:SystemBuilder:PF_DDR4:${PF_DDR4_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Actel:SystemBuilder:PF_SRAM_AHBL_AXI:${PF_SRAM_AHBL_AXI_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Microsemi:SolutionCore:mipicsi2rxdecoderPF:${mipicsi2rxdecoderPF_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:COREAHBTOAPB3:${COREAHBTOAPB3_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:COREI2C:${COREI2C_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:CoreAPB3:${CoreAPB3_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:CoreGPIO:${CoreGPIO_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:COREJTAGDEBUG:${COREJTAGDEBUG_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:CoreAHBLite:${CoreAHBLite_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:SgCore:PF_INIT_MONITOR:${PF_INIT_MONITOR_version}" -location {www.microchip-ip.com/repositories/SgCore}
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download_core -vlnv "Microsemi:MiV:MIV_RV32IMA_L1_AHB:${MIV_RV32IMA_L1_AHB_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Actel:DirectCore:COREUART:${COREUART_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Microsemi:SolutionCore:Bayer_Interpolation:${Bayer_Interpolation_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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download_core -vlnv "Microsemi:SolutionCore:Image_Enhancement:${Image_Enhancement_version}" -location {www.microchip-ip.com/repositories/DirectCore}
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#source the below tcl file to create the top level SmartDesign and generate it
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source ./src/VIDEO_KIT_TOP_recursive.tcl
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build_design_hierarchy
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#Import the constraint files and organize the Synthesize, Place and Route and Verify Timing tools
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import_files \
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-io_pdc ./src/constraint/user_io.pdc
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import_files \
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-fp_pdc ./src/constraint/user_fp.pdc
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import_files \
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-sdc ./src/constraint/user.sdc
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organize_tool_files -tool {PLACEROUTE} -file {./Libero_training1/constraint/io/user_io.pdc} -file {./Libero_training1/constraint/fp/user_fp.pdc} -file {./Libero_training1/constraint/user.sdc} -module {VIDEO_KIT_TOP::work} -input_type {constraint}
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organize_tool_files -tool {VERIFYTIMING} -file {./Libero_training1/constraint/user.sdc} -module {VIDEO_KIT_TOP::work} -input_type {constraint}
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derive_constraints_sdc
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save_project
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#Configure and run the tools Synthesize, Place and Route and Verify Timing
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#configure_tool -name {SYNTHESIZE} -params {RETIMING:true} -params {ROM_TO_LOGIC:false} -params {SYNPLIFY_TCL_FILE:../src/synplify_options.tcl}
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configure_tool -name {SYNTHESIZE} -params {ACTIVE_IMPLEMENTATION:synthesis} -params {AUTO_COMPILE_POINT:false} -params {BLOCK_MODE:false} -params {BLOCK_PLACEMENT_CONFLICTS:ERROR} -params {BLOCK_ROUTING_CONFLICTS:LOCK} -params {CDC_MIN_NUM_SYNC_REGS:2} -params {CDC_REPORT:true} -params {CLOCK_ASYNC:800} -params {CLOCK_DATA:5000} -params {CLOCK_GATE_ENABLE:false} -params {CLOCK_GATE_ENABLE_THRESHOLD_GLOBAL:1000} -params {CLOCK_GATE_ENABLE_THRESHOLD_ROW:100} -params {CLOCK_GLOBAL:2} -params {PA4_GB_COUNT:36} -params {PA4_GB_MAX_RCLKINT_INSERTION:16} -params {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT:1000} -params {RAM_OPTIMIZED_FOR_POWER:0} -params {RETIMING:true} -params {ROM_TO_LOGIC:false} -params {SEQSHIFT_TO_URAM:1} -params {SYNPLIFY_OPTIONS:} -params {SYNPLIFY_TCL_FILE:../src/synplify_options.tcl}
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run_tool -name {SYNTHESIZE}
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configure_tool -name {PLACEROUTE} -params {DELAY_ANALYSIS:MAX} -params {EFFORT_LEVEL:false} -params {GB_DEMOTION:true} -params {INCRPLACEANDROUTE:false} -params {IOREG_COMBINING:true} -params {MULTI_PASS_CRITERIA:VIOLATIONS} -params {MULTI_PASS_LAYOUT:true} -params {NUM_MULTI_PASSES:5} -params {PDPR:false} -params {RANDOM_SEED:1} -params {REPAIR_MIN_DELAY:true} -params {REPLICATION:true} -params {SLACK_CRITERIA:WORST_SLACK} -params {SPECIFIC_CLOCK:} -params {START_SEED_INDEX:3} -params {STOP_ON_FIRST_PASS:true} -params {TDPR:true}
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run_tool -name {PLACEROUTE}
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configure_tool -name {VERIFYTIMING} -params {CONSTRAINTS_COVERAGE:1} -params {FORMAT:TEXT} -params {MAX_EXPANDED_PATHS_TIMING:1} -params {MAX_EXPANDED_PATHS_VIOLATION:0} -params {MAX_PARALLEL_PATHS_TIMING:1} -params {MAX_PARALLEL_PATHS_VIOLATION:1} -params {MAX_PATHS_INTERACTIVE_REPORT:1} -params {MAX_PATHS_TIMING:5} -params {MAX_PATHS_VIOLATION:20} -params {MAX_TIMING_FAST_HV_LT:1} -params {MAX_TIMING_MULTI_CORNER:1} -params {MAX_TIMING_SLOW_LV_HT:1} -params {MAX_TIMING_SLOW_LV_LT:1} -params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MAX_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {MIN_TIMING_FAST_HV_LT:1} -params {MIN_TIMING_MULTI_CORNER:1} -params {MIN_TIMING_SLOW_LV_HT:1} -params {MIN_TIMING_SLOW_LV_LT:1} -params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} -params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} -params {MIN_TIMING_VIOLATIONS_SLOW_LV_LT:1} -params {SLACK_THRESHOLD_VIOLATION:0.0} -params {SMART_INTERACTIVE:0}
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run_tool -name {VERIFYTIMING}
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run_tool -name {GENERATEPROGRAMMINGDATA}
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#Configure Design Initialization Data and Memories
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configure_design_initialization_data -second_stage_start_address {0x00000000} -third_stage_uprom_start_address {0x00000000} -third_stage_snvm_start_address {0x00000000} -third_stage_spi_start_address {0x00000400} -third_stage_spi_type {SPIFLASH_NO_BINDING_PLAINTEXT} -third_stage_spi_clock_divider {2} -init_timeout 128 -auto_calib_timeout {3000} -broadcast_RAMs {1}
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configure_snvm -cfg_file {./src/cfg_and_mem_files/SNVM.cfg}
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#The below file sources the *.hex file generated by the SoftConsole
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configure_ram -cfg_file {./src/cfg_and_mem_files/RAM.cfg}
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save_project
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generate_design_initialization_data
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configure_tool \
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-name {GENERATEPROGRAMMINGFILE} \
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-params {program_fabric:true} \
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-params {program_security:false} \
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-params {program_snvm:true} \
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-params {sanitize_snvm:false}
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run_tool -name {GENERATEPROGRAMMINGFILE}
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#Generate the Programming job file
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export_prog_job \
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-job_file_name {VIDEO_KIT_TOP} \
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-export_dir {.} \
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-bitstream_file_type {TRUSTED_FACILITY} \
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-bitstream_file_components {FABRIC_SNVM} \
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-zeroization_likenew_action 0 \
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-zeroization_unrecoverable_action 0 \
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-program_design 1 \
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-program_spi_flash 0 \
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-include_plaintext_passkey 0 \
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-design_bitstream_format {PPD} \
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-prog_optional_procedures {} \
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-skip_recommended_procedures {} \
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-sanitize_snvm 0
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save_project

‎Training1/Libero/readme.txt‎

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This training can be regenerated on Windows using Cygwin or on Linux.
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-----------------------------------------------------------------------
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Windows (Cygwin):
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-----------------------------------------------------------------------
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1. Open Cygwin by running the .bat file from the SmartHLS installation directory, e.g.:
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C:\Microchip\Libero_SoC_v2022.2\SmartHLS-2022.2\cygwin64\Cygwin.bat
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2. Navigate to this current directory, e.g.:
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cd /cygdrive/c/training_libero_projects/training1
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Note that C:\ is replaced by /cygdrive/c/
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3. Run the Bash script to generate the HLS example designs:
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bash run_shls_on_examples.sh
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4. When this completes, use Libero to generate the project. This can be
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done from the shell or the IDE.
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4a. Shell: From the same directory, run the command:
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libero SCRIPT:libero_flow.tcl LOGFILE:output.log &
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4b. IDE:
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- Open Libero
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- Go to File -> Execute Script
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- Choose libero_flow.tcl under "Script file". There are no arguments needed.
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- Click 'Run'
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-----------------------------------------------------------------------
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Linux:
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-----------------------------------------------------------------------
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1. First run the Bash script to generate the HLS example designs:
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bash run_shls_on_examples.sh
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2. When this completes, use Libero to generate the project. This can be
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done from the shell or the IDE.
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2a. Shell: From the same directory, run the command:
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libero SCRIPT:libero_flow.tcl LOGFILE:output.log &
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2b. IDE:
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- Open Libero
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- Go to File -> Execute Script
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- Choose libero_flow.tcl under "Script file". There are no arguments needed.
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- Click 'Run'

‎Training1/Libero/run_shls_on_examples.sh‎

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# This script should be run first to run shls on the required examples.
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# After this script completed, follow the remaining instructions in the
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# readme to run libero on the generated designs.
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echo ""
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echo "Running shls hw on Canny_FIFO_Switch"
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echo ""
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cd ../Canny_FIFO_Switch
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shls hw
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echo ""
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echo "Running shls hw on Gaussian_FIFO_Pipelined"
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echo ""
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cd ../Gaussian_FIFO_Pipelined
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shls hw
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echo ""
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echo "Running shls hw on RGB2YCbCr"
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echo ""
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cd ../RGB2YCbCr
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shls hw
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echo ""
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echo "Running shls hw on YCbCr2RGB"
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echo ""
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cd ../YCbCr2RGB
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shls hw
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echo ""
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echo "Running shls hw on alpha_blend"
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echo ""
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cd ../alpha_blend
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shls hw
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cd ../Libero/
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echo ""
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echo "Now run Libero by following the remaining steps in readme.txt."
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echo ""

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